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| ds07-13505-5e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16f MB90246a series MB90246a n description the MB90246a series is a 16-bit microcontroller optimum to control mechatronics such as a hard disk drive unit. the instruction set of f 2 mc-16f cpu core inherits at architecture of f 2 mc*-16/16h family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word data (32-bit). the MB90246a series contains a production addition unit as peripheral resources for enabling easy implementation of functions supported by iir and fir digital filters. it also supports a wealth of peripheral functions including: - an 8/10-bit a/d converter having eight channels; - an 8-bit d/a converter having three channels; - uart; - an 8-bit pwm timer having four channels; - a timer having three plus one channels; - an input capture (icu) having two channels; and - a dtp/external interrupt circuit having four channels. * : f 2 mc stands for fujitsu flexible microcontroller. n package 100-pin plastic lqfp (fpt-100p-m05)
2 MB90246a series n features ?clock operating clock can be selected from divided-by-2, 4, 8 or 32 of oscillation (at oscillation of 32 mhz, 1 mhz to 16 mhz). minimum instruction execution time of 62.5 ns (at machine clock of 16 mhz) ? cpu addressing space of 16 mbytes internal addressing of 24-bit external accessing can be performed by selecting 8/16-bit bus width (external bus mode) ? instruction set optimized for controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) high code efficiency enhanced precision calculation realized by the 32-bit accumulator signed multiplication/division instruction ? instruction set designed for high level language (c) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? enhanced execution speed 8-byte instruction queue ? enhanced interrupt function priority levels: 8 levels external interrupt input ports: 4 ports ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os) ? low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) hardware stand-by mode gear function ?process cmos technology ? i/o port general-purpose i/o ports (cmos): 38 general-purpose i/o ports (ttl): 11 general-purpose i/o ports (n-ch open-drain): 8 total: 57 ?timer timebase timer/watchdog timer: 1 channel 8-bit pwm timer: 4 channels 16-bit re-load timer: 3 channels ? 16-bit i/o timer 16-bit free-run timer: 1 channel input capture (icu): 2 channels ? i/o simple serial interface clock synchronized transmission can be used. ? uart: 1 channel clock asynchronized or clock synchronized serial transmission can be selectively used. ? dtp/external interrupt circuit: 4 channels a module for starting extended intelligent i/o service (ei 2 os) and generating an external interrupt triggered by an external input. (continued) 3 MB90246a series (continued) ? delayed interrupt generation module generates an interrupt request for switching tasks. ? 8/10-bit a/d converter: 8 channels 8-bit or 10-bit resolution can be selectively used. starting by an external trigger input. ? 8-bit d/a converter resolution: 8 bits 3 channels ? dsp interface for the iir filter function dedicated to iir calculation up to eight items of results of signed multiplication of 16 16 bits are added. execution time of : 0.625 m s (when oscillation is 32 mhz and when n = m =3) up to three n and m values can be set at your disposal. yk = s bn yk C n + s am xk C m nm n = 0 m = 0 4 MB90246a series n product lineup (continued) mb90v246 classification mass-produced product evaluation product rom size none ram size 4 k 8 bits 6 k 8 bits cpu functions the number of instructions: 412 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 4 bits, 8 bits, 16 bits, 32 bits minimum execution time: 62.5 ns (at machine clock of 16 mhz) interrupt processing time: 1.0 m s (at machine clock of 16 mhz, minimum value) ports general-purpose i/o ports (cmos output): 38 general-purpose i/o ports (ttl input): 11 general-purpose i/o ports (n-ch open-drain output): 8 total: 57 timebase timer 18-bit counter interrupt interval: 0.256 ms, 1.024 ms, 4.096 ms, 16.384 ms (at oscillation of 32 mhz) watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 28.67 ms, 57.34 ms (at oscillation of 32 mhz, minimum value) 8/16-bit pwm timer number of channels: 4 pulse interval: 0.25 m s to 32.77 ms (at oscillation of 32 mhz) 16-bit re-load timer number of channels: 3 16-bit re-load timer operation interval: 125 ns to 131 ms (at machine clock of 16 mhz) external event count can be performed. 16-bit i/o timer 16-bit free-run timer number of channel: 1 overflow interrupts or intermediate bit interrupts may be generated. input capture (icu) number of channel: 2 rewriting a register value upon a pin input (rising, falling, or both edges) i/o simple serial interface number of channels: 2 clock synchronized transmission (62.5 kbps to 8 mbps) uart clock asynchronized transmission (2404 bps to 500 kbps) clock synchronized transmission (250 kbps to 2 mbps) transmission can be performed by bi-directional serial transmission or by master/slave connection. dtp/external interrupt circuit number of inputs: 4 started by a rising edge, a falling edge, an h level input, or an l level input. external interrupt circuit or extended intelligent i/o service (ei 2 os) can be used. delayed interrupt generation module an interrupt generation module for switching tasks used in real-time operating systems. MB90246a item part number 5 MB90246a series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) assurance for the mb90v246 is given only for operation with a tool at a power voltage of 4.5 v to 5.5 v, an operating temperature of 0 to 70 degrees centigrade, and an clock frequency of 1.6 mhz to 32 mhz. note: a 64-word ram for product addition is supported in addition to the above rams. n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products memory size in evaluation with an evaluation chips, note the difference between the evaluation chip and the chip actually used. the ram size is 4 kbytes for the MB90246a, and 6 kbytes for the mb90v246. mb90v246 8/10-bit a/d converter conversion precision: 10-bit or 8-bit can be selectively used. number of inputs: 8 one-shot conversion mode (converts selected channel only once) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8-bit d/a converter number of channels: 3 resolution: 8 bits based on the r-2r system dsp interface for the iir filter function dedicated to iir calculation up to 8 items of results of signed multiplication of 16 16 bits are added. execution time of : 0.625 m s (when oscillation is 32 mhz and when n = m = 3) up to three n and m values can be set at your disposal. low-power consumption (stand-by) mode sleep/stop/hardware stand-by/gear function process cmos power supply voltage for operation* 4.5 v to 5.5 v package MB90246a mb90v246 fpt-100p-m05 pga-256c-a02 MB90246a yk = s bn yk C n + s am xk C m nm n = 0 m = 0 item part number 6 MB90246a series n pin assignment p71/asr1 p72 p73 p74/tin0/tot0 p75/tin1/tot1 p76/tin2/tot2 av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 dvrh dvrl md0 md1 md2 hst rst p54/wrh p53/hrq p52/hak p51/rdy p50/clk pa5/sck2 pa4/sod2 pa3/sid2 pa2/sck1 pa1/sod1 pa0/sid1 p96/sck0 p95/sod0 p94/sid0 p93/int3/pwm3 p92/int2/atg p91/int1 p90/int0 p87/pwm2 p86/pwm1 p85/pwm0 p84/dao2 p83/dao1 p82/dao0 a02 a03 a04 a05 a06 a07 a08 a09 v ss a10 a11 a12 a13 a14 a15 p40/a16 p41/a17 p42/a18 p43/a19 p44/a20 v cc p45/a21 p46/a22 p47/a23 p70/asr0 (top view) (fpt-100p-m05) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a01 a00 p17/d15 p16/d14 p15/d13 p14/d12 p13/d11 p12/d10 p11/d09 p10/d08 p07 p06 p05 p04 p03 p02 p01 p00 v cc x1 x0 v ss p57 p56/rd p55/wr /wrl 7 MB90246a series n pin description pin no. pin name circuit type function lqfp* 80 x0 a this is a crystal oscillator pin. 81 x1 47 to 49 md0 to md2 c this is an input pin for selecting operation modes. connect directly to v cc or v ss . 75 rst b this is external reset request signal. 50 hst c this is a hardware stand-by input pin. 91 to 98 p10 to p17 d this is a general-purpose i/o port. this function is valid in the 8-bit mode where the external bus is valid. d08 to d15 this is an i/o pin for the upper 8-bit of the external address data bus. this function is valid in the 16-bit mode where the external bus is valid. 16 to 20, 22 to 24 p40 to p44, p45 to p47 e this is a general-purpose i/o port. this function becomes valid in the bit where the upper address control register is set to select a port. a16 to a20, a21 to a23 this is an output pin for the upper 8-bit of the external address bus. this function is valid in the mode where the external bus is valid and the upper address control register is set to select an address. 70 p50 e this is a general-purpose i/o port. this function becomes valid when the clk output is disabled. clk this is a clk output pin. this function becomes valid when clk output is enabled. 71 p51 d this is a general-purpose i/o port. this function becomes valid when the external ready function are disabled. rdy this is a ready input pin. this function becomes valid when the external ready function is enabled. 72 p52 d this is a general-purpose i/o port. this function becomes valid when the hold function are disabled. hak this is a hold acknowledge output pin. this function becomes valid when the hold function is enabled. 73 p53 d this is a general-purpose i/o port. this function becomes valid when the hold function are disabled. hrq this is a hold request input pin. this function becomes valid when the hold function is enabled. 74 p54 e this is a general-purpose i/o port. this function becomes valid, in the external bus 8-bit mode, or wrh pin output is disabled. wrh this is a write strobe output pin for the upper 8-bit of the data bus. this function becomes valid when the external bus 16-bit mode is selected, and wrh output pin is enabled. * : fpt-100p-m05 (continued) 8 MB90246a series pin no. pin name circuit type function lqfp* 76 p55 e this is a general-purpose i/o port. this function becomes valid when wrl /wr pin output is disabled. wr this is a write strobe output pin for the lower 8-bit of data bus. this function becomes valid when wrl /wr pin output is enabled. wrl is used for holding the lower 8-bit for write strobe in 16-bit access operations, while wr is used for holding 8-bit data for write strobe in 8-bit access operations. wrl 77 p56 e this pin cannot be used as a general-purpose port. rd this is a read strobe output pin for the data bus. this function is valid in the mode where the external bus is valid. 78,28,27 p57,p73,p72 e this is a general-purpose i/o port. 36 to 39, 41 to 44 p60 to p63, p64 to p67 g this is an i/o port of an n-ch open-drain type. when the data register is read by a read instruction other than the modify write instruction with the corresponding bit in ader set at 0, the pin level is acquired. the value set in the data register is output to the pin as is. an0 to an3, an4 to an7 this is an analog input pin of the 8/10-bit a/d converter. when using this input pin, set the corresponding bit in ader at 1. also, set the corresponding bit in the data register at 1. 25 p70 e this is a general-purpose i/o port. asr0 this is a data input pin for input capture 0. because this input is used as required when the input capture 0 is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. 26 p71 e this is a general-purpose i/o port. asr1 this is a data input pin of input capture 1. because this input is used as required when input capture 1 is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. 29 to 31 p74 to p76 e this is a general-purpose i/o port. this function becomes valid when outputs from 16-bit re-load timer 0 C 2 are disabled. tin0 to tin 2 this is an input pin of 16-bit timer. because this input is used as required whin 16-bit timer 0 - 2 is performing input operations,and it is necessary to stop outputs by other functions unless such outputs are made intentionally. tot0 to tot2 these are output pins for 16-bit re-load timer 0 and 1. this function becomes valid when output from 16-bit re-load timer 0 C 2 are enabled. 51 to 53 p82 to p84 h this is a general-purpose i/o port. this function becomes valid when data output from 8-bit d/a converter 0 C 2 are disabled. dao0 to dao2 this is an output pin of 8-bit d/a converter. this function becomes valid when data output from 8-bit d/a converter 0 C 2 are enabled. * : fpt-100p-m05 (continued) 9 MB90246a series pin no. pin name circuit type function lqfp* 54 to 56 p85 to p87 e this is a general-purpose i/o port. this function becomes valid when output from pwm0 C pwm2 are disabled. pwm0 to pwm2 this is an output pin of 8-bit pwm timer. this function becomes valid when output from pwm0 C pwm2 are enabled. 57, 58 p90, p91 f this is a general-purpose i/o port. int0, int1 this is a request input pin of the dtp/external interrupt circuit ch.0 and 1. because this input is used as required when the dtp/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. 59 p92 e this is a general-purpose i/o port. int2 this is an input pin of the dtp/external interrupt circuit ch.2. because this input is used as required when the dtp/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. atg this is a trigger input pin of the 8/10-bit a/d converter. because this input is used as requited when the 8/10-bit a/d converter is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. 60 p93 e this is a general-purpose i/o port. this function is always valid. this function becomes valid when output from pwm3 is disabled. int3 this is a request input of the dtp/external interrupt circuit ch. 3. because this input is used as required when the dtp/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such output are made intentionally. pwm3 this is an output pin of 8-bit pwm timer. this function becomes valid when output from pwm3 is enabled. 61 p94 e this is a general-purpose i/o port. this function becomes valid when serial data output from uart is disabled. sid0 this is a serial data i/o pin of uart. this function becomes valid when serial data output from uart is enabled. because this input is used as required when uart is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. * : fpt-100p-m05 (continued) 10 MB90246a series pin no. pin name circuit type function lqfp* 62 p95 e this is a general-purpose i/o port. this function becomes valid when data output from uart is disabled. sod0 this is a data output pin of uart. this function becomes valid when data output from uart is enabled. 63 p96 e this is a general-purpose i/o port. this function becomes valid when clock output from uart is disabled. sck0 this is a clock i/o pin of uart. this function becomes valid when clock output from uart is enabled. because this input is used as required when uart is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. 1 to 6, 100, 99 a02 to a07, a01, a00 e this is an output pin for the lower 8-bit of the external address bus. 7, 8, 10 to 15 a08, a09, a10 to a15 e this is an output pin for the middle 8-bit of the external address bus. this function is valid in the mode where the external bus is valid and the middle address control refister is set to select an address. 64 pa0 e this is a general-purpose i/o port. sid1 this is a data input pin of i/o simple serial interface 1. because this input is used as required when i/o simple serial interface 1 is performing input operations, and it is necessarey to stop outputs by other functions unless such outputs are made intentionally. 65 pa1 e this is a general-purpose i/o port. this function becomes valid when data output from i/o simple serial interface 1 is disabled. sod1 this is a data output pin of i/o simple serial interface 1. this function becomes valid when data output from i/o simple serial interface 1 is enabled. 66 pa2 e this is a general-purpose i/o port. this function becomes valid when clock output from i/o simple serial interface 1 is disabled. sck1 this is a clock output pin of i/o simple serial interface 1. this function becomes valid when clock output from i/o simple serial interface 1 is enabled. * : fpt-100p-m05 (continued) 11 MB90246a series (continued) pin no. pin name circuit type function lqfp* 67 pa3 e this is a general-purpose i/o port. sid2 this is a data input pin of i/o simple serial interface 2. because this input is used as required when is performing input operations, and it is i/o simple serial interface 2 necessarey to stop outputs by other functions unless such outputs are made intentionally. 68 pa4 e this is a general-purpose i/o port. this function becomes valid when data output from i/o simple serial interface 2 is disabled. sod2 this is a data output pin of i/o simple serial interface 2. this function becomes valid when data output from i/o simple serial interface 2 is enabled. 69 pa5 e this is a general-purpose i/o port. this function becomes valid when clock output from i/o simple serial interface 2 is disabled. sck2 this is clock output pin of i/o simple serial interface 2. this function becomes valid when clock output from i/o simple serial interface 2 is enabled. 83 to 90 d00 to d07 d this is an i/o pin for the lower 8-bit of the external data bus. 21, 82 v cc power supply this is power supply to the digital circuit. 9, 40, 79 v ss power supply this is a ground level of the digital circuit. 32 av cc power supply this is power supply to the analog circuit. make sure to turn on/turn off this power supply with a voltage exceeding av cc applied to v cc . 33 avrh power supply this is a reference voltage input to the a/d converter. make sure to turn on/turn off this power supply with a voltage exceeding avrh applied to av cc . 34 avrl power supply this is a reference voltage input to the a/d converter. 35 av ss power supply this is a ground level of the analog circuit. 45 dvrh power supply this is an external reference power supply pin for the d/a converter. 46 dvrl power supply this is an external reference power supply pin for the d/a converter. * : fpt-100p-m05 12 MB90246a series n i/o circuit type (continued) type circuit remarks a ? for oscillation of 32 mhz ? oscillation feedback resistor approx. 1 m w b ? cmos level hysteresis input (without stand-by control) ? pull-up resistor approx. 50 k w c ? cmos level hysteresis input (without stand-by control) d ? cmos level output ? ttl level input (with stand-by control) x1 x0 n-ch clock input clock suspension p-ch type trigger cmos digital input v ss v cc n-ch type trigger r cmos v ss v cc digital input p-ch type trigger n-ch type trigger r digital input p-ch n-ch standby control signal digital output digital output r ttl 13 MB90246a series (continued) type circuit remarks e ? cmos level output ? cmos level hysteresis input (with stand-by control) f ? cmos level input ? cmos level hysteresis input (with stand-by control (during interrupt disable)) g ? n-ch open-drain ? cmos level output ? cmos level hysteresis input ? analog input (with analog control) h ? cmos level output ? analog output ? cmos level hysteresis input (with stand-by control) p-ch n-ch digital output digital output digital input standby control signal r cmos p-ch n-ch digital input r digital output digital output standby control signal (during interrupt disable) cmos ader digital input r digital output analog input p-ch n-ch digital input r digital output digital output cmos standby control signal analog input 14 MB90246a series n handling devices 1. make sure that the voltage not exceed the maximum rating (to avoid a latch-up) in cmos ics, a latch-up phenomenon is caused when an voltage exceeding v cc or an voltage below v ss is applied to input or output pins or a voltage exceeding the rating is applied across v cc and v ss . when a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. to avoid the latch-up, make sure that the voltage not exceed the maximum rating. in turning on/turning off the analog power supply, make sure the analog power voltage (av cc , avrh) and analog input voltages not exceed the digital voltage (v cc ). 2. connection of unused pins leaving unused pins open may result in abnormal operations. clamp the pin level by connecting it to a pull-up or a pull-down resistor. 3. notes on using external clock in using the external clock, drive x0 pin only and leave x1 pin unconnected. 4. power supply pins in products with multiple v cc or v ss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pin near the device. 5. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with an grand area for stabilizing the operation. ? using external clock x0 x1 open MB90246a series 15 MB90246a series 6. turning-on sequence of power supply to a/d converter, d/a converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl), d/a converter power supply and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage not exceed avrh or av cc (turning on/off the analog and digital supplies simultaneously is acceptable). 7. connection of unused pins of a/d converter connect unused pins of a/d converter to av cc = v cc , av ss = avrh = avrl = v ss . 8. mov @al, ah, movw @al, ah instructions when the above instruction is performed to i/o space, an unnecessary writing operation may be performed (#ff, #ffff) in the internal bus. use the compiler function for inserting an nop instruction before the above instructions to avoid the writing operation. accessing ram space with the above instruction does not cause any problem. 9. initialization in the device, there are internal registers which is initialized only by a power-on reset. to initialize these registers turning on the power again. 10.external reset input to reset the internal securely, l level input to the rst pin must be at least 5 machine cycle. 11.hst pin make sure hst pin is set to h level when turn on the power supply. also make sure hst pin is never set to l level, when rst pin is set to l level. 12.clk pin a case 32 mhz x1 x0 p50/clk* stop clk output p50 output p50 input 2 deviding circuit to the inside *: at p50/clk pin in the external bus mode, clk output is selected as an initial value. 16 MB90246a series n block diagram port 1 f 2 mcC16f. cpu clock control block (including timebase timer) external bus interface 16-bit re-load timer input compare (icu) interrupt controller port 8 8-bit d/a converter internal data bus uatr port a dtp/external interrupt circuit 0, 1, 2 dsp interface for the iir filter ram x0 x1 rst hst p10/d08 to p17/d15 p40/a16 to p47/a23 p50/clk p57 p56/rd p55/wr /wrl p54/wrh p53/hrq p52/hak p51/rdy p70/asr0 p71/asr1 p82/dao0 to p84/dao2 dvrh dvrl p94/sid0 p95/sod0 p96/sck0 pa0/sid1 pa1/sod1 pa2/sck1 8 8 8 16 2 3 3 3 3 8 13 a00 to a15 d00 to d07 port 4, 5 port 7 3 16-bit i/o timer 3 2 16-bit free-run timer port 9 8/10-bit a/d converter 8 8 port 6 p72 p73 p74/tin0/tot0 to p76/tin2/tot2 p90/int0 p91/int1 p92/int2/atg avrh avrl av cc av ss p60/an0 to p67/an7 other pins md0 to md2, v cc ,v ss p85/pwm0 to p87/pwm2 p93/int3/pwm3 8-bit pwm timer 4 channels 3 3 port 9 dtp/external interrupt circuit 3 2 2 4 i/o simple serial interface pa3/sid2 pa4/sod2 pa5/sck2 17 MB90246a series memory map the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit of bank ff and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the rom without stating far. 000100 h 0000c0 h 000000 h ram register external rom external bus mode : internal access memory : enternal access memory i/o external area external area external area i/o 001980 h 001900 h 001100 h ffffff h 18 MB90246a series n f 2 mc-16f cpu programming model (1) dedicated registers : accumlator (a) dual 16-bit register used for storing results of calculation etc. the two 16-bit registers can be combined to be used as a 32-bit register. : additional data bank register (adb) the 8-bit register for displaying the additional data. : user stack pointer (usp) the 16-bit pointer for containing a user stack address. : user stack bank register (usb) the 8-bit register for displaying the user stack space. : system stack pointer (ssp) the 16-bit pointer for displaying the status of the system stack address. : processor status (ps) the 16-bit register for displaying the system status. : program bank register (pcb) the 8-bit register for displaying the program space. : data bank register (dtb) the 8-bit register for displaying the data space. : program counter (pc) the 16-bit register for displaying storing location of the current instruction code. : direct page register (dpr) the 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. : system stack bank register (ssb) the 8-bit register for displaying the system stack space. ah al usp ssp dpr pcb dtb usb ssb adb ps pc 8-bit 16-bit 32-bit uspcu sscpu uspcl sspcl : user stack upper limit register (uspcu) the 16-bit register for specifying the upper limit of the user stack. : system stack upper limit register (sspcu) the 16-bit register for specifying the upper limit of the system stack. : user stack lower limit register (uspcl) the 16-bit register for specifying the lower limit of the user stack. : system stack lower limit register (sspcl) the 16-bit register for specifying the lower limit of the system stack. 19 MB90246a series (2) general-purpose registers (3) processor status (ps) maximum of 32 banks 000180 h + (rp 10 h ) r7 r5 r3 r1 r6 r4 r2 r0 rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 rw3 rw2 rw1 rw0 16-bit ilm rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ilm2 b4 ilm1 ilm0 b3 b2 b1 b0 istnzvc 00 000 0 00 1 0xxx x x ps initial value x : indeterminate : unused 20 MB90246a series n i/o map (continued) address abbreviated register name register name read/ write resource name initial value 000000 h (system reservation area)* 1 000001 h pdr1 port 1 data register r/w! port 1 x x x x x x x x b 000002 h (system reservation area)* 1 000003 h 000004 h pdr4 port 4 data register r/w! port 4 x x x x x x x x b 000005 h pdr5 port 5 data register r/w! port 5 x x x x x x x x b 000006 h pdr6 port 6 data register r/w! port 6 1 1 1 1 1 1 1 1 b 000007 h pdr7 port 7 data register r/w! port 7 C x x x x x x x b 000008 h pdr8 port 8 data register r/w! port 8 x x x x x x C C b 000009 h pdr9 port 9 data register r/w! port 9 C x x x x x x x b 00000a h pdra port a data register r/w! port a C C x x x x x x b 00000b h to 00000f h (vacancy) 000010 h (system reservation area)* 1 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h (system reservation area)* 1 000013 h 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ader analog input enable register r/w port 6, 8/10-bit a/d converter 11111111 b 000017 h ddr7 port 7 direction register r/w port 7 C 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 0 0 0 0 0 0 C C b 000019 h ddr9 port 9 direction register r/w port 9 C x x x x x x x b 00001a h ddra port a direction register r/w port a C C 0 0 0 0 0 0 b 00001b h to 00001f h (vacancy) 000020 h scr1 serial control status register 1 r/w i/o simple serial interface 1 10000000 b 000021 h ssr1 serial status register 1 r C C C C C C C 1 b 000022 h sdr1l serial data register 1 (l) r/w x x x x x x x x b 000023 h sdr1h serial data register 1 (h) r/w x x x x x x x x b 21 MB90246a series (continued) address abbreviated register name register name read/ write resource name initial value 000024 h scr2 serial control status register 2 r/w i/o simple serial interface 2 10000000 b 000025 h ssr2 serial status register 2 r C C C C C C C 1 b 000026 h sdr2l serial data register 2 (l) r/w x x x x x x x x b 000027 h sdr2h serial data register 2 (h) r/w x x x x x x x x b 000028 h umc mode control register r/w uart 00000100 b 000029 h usr status register r/w 00010000 b 00002a h uidr/ uodr input data register/ output data register r/w xxxxxxxx b 00002b h urd rate and data register r/w 0 0 0 0 0 0 0 0 b 00002c h pwmc3 pwm3 operating mode control register r/w 8-bit pwm timer 3 00000xx1 b 00002d h (vacancy) 00002e h prll3 pwm3 re-road register (l) r/w 8-bit pwm timer 3 xxxxxxxx b 00002f h prlh3 pwm3 re-road register (h) r/w x x x x x x x x b 000030 h enir dtp/interrupt enable register r/w dtp/external interrupt circuit CCCC0000 b 000031 h eirr dtp/interrupt factor register r/w C C C C 0 0 0 0 b 000032 h elvr request level setting register r/w 0 0 0 0 0 0 0 0 b 000033 h (vacancy) 000034 h pwmc0 pwm0 operating mode control register r/w 8-bit pwm timer 0 00000xx1 b 000035 h (vacancy) 000036 h prll0 pwm0 re-road register (l) r/w 8-bit pwm timer 0 xxxxxxxx b 000037 h prlh0 pwm0 re-road register (h) r/w x x x x x x x x b 000038 h pwmc1 pwm1 operating mode control register r/w 8-bit pwm timer 1 00000xx1 b 000039 h (vacancy) 00003a h prll1 pwm1 re-road register (l) r/w 8-bit pwm timer 1 xxxxxxxx b 00003b h prlh1 pwm1 re-road register (h) r/w x x x x x x x x b 00003c h pwmc2 pwm2 operating mode control register r/w 8-bit pwm timer 2 00000xx1 b 00003d h (vacancy) 00003e h prll2 pwm2 re-road register (l) r/w 8-bit pwm timer 2 xxxxxxxx b 00003f h prlh2 pwm2 re-road register (h) r/w x x x x x x x x b 000040 h tmcsr0 timer control status register 0 lower digits r/w 16-bit re-load timer 0 00000000 b 000041 h timer control status register 0 upper digits r/w CCCC0000 b 22 MB90246a series (continued) address abbreviated register name register name read/ write resource name initial value 000042 h tmr0 16-bit timer register 0 r 16-bit re-load timer 0 xxxxxxxx b 000043 h xxxxxxxx b 000044 h tmrlr0 16-bit re-load register 0 r/w xxxxxxxx b 000045 h xxxxxxxx b 000046 h (vacancy) 000047 h 000048 h tmcsr1 timer control status register 1 lower digits r/w 16-bit re-load timer 1 00000000 b 000049 h timer control status register 1 upper digits r/w CCCC0000 b 00004a h tmr1 16-bit timer register 1 r xxxxxxxx b 00004b h xxxxxxxx b 00004c h tmrlr1 16-bit re-load register 1 r/w xxxxxxxx b 00004d h xxxxxxxx b 00004e h (vacancy) 00004f h 000050 h tmcsr2 timer control status register 2 lower digits r/w 16-bit re-load timer 2 00000000 b 000051 h timer control status register 2 upper digits r/w CCCC1111 b 000052 h tmr2 16-bit timer register 2 r xxxxxxxx b 000053 h xxxxxxxx b 000054 h tmrlr2 16-bit re-load register 2 r/w xxxxxxxx b 000055 h xxxxxxxx b 000056 h to 000059 h (vacancy) 00005a h dadr0 d/a data register 0 r/w 8-bit d/a converter 0 xxxxxxxx b 00005b h dacr0 d/a control register 0 r/w C C C C C C C 0 b 00005c h dadr1 d/a data register 1 r/w 8-bit d/a converter 1 xxxxxxxx b 00005d h dacr1 d/a control register 1 r/w C C C C C C C 0 b 00005e h dadr2 d/a data register 2 r/w 8-bit d/a converter 2 xxxxxxxx b 00005f h dacr2 d/a control register 2 r/w C C C C C C C 0 b 000060 h ipcp0 input capture register 0 r 16-bit i/o timer (input capture 0, 1) xxxxxxxx b 000061 h xxxxxxxx b 000062 h ipcp1 input capture register 1 r xxxxxxxx b 000063 h xxxxxxxx b 000064 h ics0 input capture control register r/w 0 0 0 0 0 0 0 0 b 23 MB90246a series (continued) address abbreviated register name register name read/ write resource name initial value 000065 h to 00006b h (vacancy) 00006c h tcdt timer data register r/w 16-bit i/o timer (16-bit free-run timer) 00000000 b 00006d h 00000000 b 00006e h tccs timer control status register r/w 0 0 0 0 0 0 0 0 b 00006f h (vacancy) 000070 h adcsl a/d control status register lower digits r/w 8/10-bit a/d converter 000C0000 b 000071 h adcsh a/d control status register upper digits r/w C000CC00 b 000072 h adct conversion time setting register r/w xxxxxxxx b 000073 h xxxxxxxx b 000074 h adtl0 a/d data register 0 r xxxxxxxx b 000075 h adth0 r CCCCCC* * b 000076 h adtl1 a/d data register 1 r xxxxxxxx b 000077 h adth1 r CCCCCC* * b 000078 h adtl2 a/d data register 2 r xxxxxxxx b 000079 h adth2 r CCCCCC* * b 00007a h adtl3 a/d data register 3 r xxxxxxxx b 00007b h adth3 r CCCCCC* * b 00007c h to 00007f h (vacancy) 000080 h mcsr product addition control status register lower digits r/w dsp interface for the iir filter xxx0xxx0 b 000081 h product addition control status register digits r/w Cxxxxxxx b 000082 h mccrl product addition continuation control register lower digits r/w 00000000 b 000083 h mccrh product addition continuation control register upper digits r/w CCCCCC00 b 000084 h mdorl production addition output register r xxxxxxxx b 000085 h xxxxxxxx b 000086 h mdorm r xxxxxxxx b 000087 h mdorh r xxxxxxxx b 000088 h xxxxxxxx b 24 MB90246a series (continued) address abbreviated register name register name read/ write resource name initial value 000089 h to 00008f h (vacancy) 000090 h to 00009e h (system reservation area)* 1 00009f h dirr delayed interrupt factor generation/ cancellation register r/w delayed interrupt generation module CCCCCCC0 b 0000a0 h stbyc standby control register r/w low-power consumption (stand-by) mode 0001xxxx b 0000a1 h to 0000a3 h (system reservation area)* 1 0000a4 h hacr upper address control register w external bus pin *2 0000a5 h epcr external pin control register w *2 0000a8 h wdtc watchdog timer control register r/w watchdog timer x x x x x x x x b 0000a9 h tbtc timebase timer control register r/w timebase timer C x x 0 0 1 0 0 b 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h to 0000ff h (external area)* 3 25 MB90246a series descriptions for read/write r/w: readable and writable r: read only w: write only r/w!: bits for reading operation only or writing operation only are included. refer to the register lists for specific resource for detailed information. descriptions for initial value 0 : the initial value of this bit is 0. 1 : the initial value of this bit is 1. x : the initial value of this bit is indeterminate. C : this bit is not used. the initial value is indeterminate. * : the storage type varies with the value of the adcsh creg bit. *1: access prohibited. *2: the initial value varies with bus mode. *3: this area is the only external access area having an address of 0000ff h or lower. access to any of the addresses specified as reserved areas in the table is handled as if an internal area were accessed. a signal for accessing an external bus is not generated. *4: when a register described as r/w! or w in the read/write column is accessed by a bit setting instruction or other read modify write instructions, the bit pointed to by the instruction becomes a set value. if a bit is writable by other bits, however, malfunction occurs. you must not, therefore, access that register using these instructions. note: for bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. note that the values are different from reading results. 26 MB90246a series n interrupt factors, interrupt vectors, interrupt control register : can be used : can not be used : can be used. with extended intelligent i/o service (ei 2 os) stop function at abnormal operation. : can be used if interrupt request using icr are not commonly used. interrupt source ei 2 os support interrupt vector interrupt control register priority* 2 number address icr address reset # 08 08 h ffffdc h high int9 instruction # 09 09 h ffffd8 h exception # 10 0a h ffffd4 h dtp/external interrupt circuit channel 0 # 11 0b h ffffd0 h icr00 0000b0 h dtp/external interrupt circuit channel 1 # 13 0d h ffffc8 h icr01 0000b1 h input capture (icu) channel 0 # 15 0f h ffffc0 h icr02 0000b2 h input capture (icu) channel 1 # 17 11 h ffffb8 h icr03 0000b3 h i/o simple serial interface channel 2 # 18 12 h ffffb4 h dtp/external interrupt circuit channel 2 # 19 13 h ffffb0 h icr04 0000b4 h dtp/external interrupt circuit channel 3 # 21 15 h ffffa8 h icr05 0000b5 h 16-bit free-run timer overflow # 23 17 h ffffa0 h icr06 0000b6 h timebase timer interval interrupt # 25 19 h ffff98 h icr07 0000b7 h 16-bit re-load timer channel 0 # 27 1b h ffff90 h icr08* 1 0000b8 h 8-bit pwm timer channel 0 # 28 1c h ffff8c h 16-bit re-load timer channel 1 # 29 1d h ffff88 h icr09* 1 0000b9 h 8-bit pwm timer channel 1 # 30 1e h ffff84 h 16-bit re-load timer channel 2 # 31 1f h ffff80 h icr10* 1 0000ba h 8-bit pwm timer channel 2 # 32 20 h ffff7c h 8/10-bit a/d converter measurement complete # 33 21 h ffff78 h icr11* 1 0000bb h 8-bit pwm timer channel 3 # 34 22 h ffff74 h i/o simple serial interface channel 1 # 35 23 h ffff70 h icr12 0000bc h uart transmission complete # 37 25 h ffff68 h icr13 0000bd h uart reception complete # 39 27 h ffff60 h icr14 0000be h delayed interrupt generation module # 42 2a h ffff54 h icr15 0000bf h stack fault # 255 ff h fffc00 h low 27 MB90246a series *1: ? interrupt levels for peripherals that commonly use the icr register are in the same level. ? when the extended intelligent i/o service (ei 2 os) is specified in a peripheral device commonly using the icr register, only one of the functions can be used. ? when the extended intelligent i/o service (ei 2 os) is specified for one of the peripheral functions, interrupts can not be used on the other function. *2: the level shows priority of same level of interrupt invoked simultaneously. 28 MB90246a series n peripherals 1. i/o port (1) input/output port ports 1, 4, 5, 7 to 9, a are general-purpose i/o ports having a combined function as an external bus pin and a resource input. the input output ports function as general-purpose i/o port only in the single-chip mode. in the external bus mode, the ports are configured as external bus pins, and part of pins for port 4 can be configured as general-purpose i/o port by setting the bus control signal select register (ecsr). ? operation as output port the pin is configured as an output port by setting the corresponding bit of the ddr register to 1. writing data to pdr register when the port is configured as output, the data is retained in the output latch in the pdr and directly output to the pin. the value of the pin (the same value retained in the output latch of pdr) can be read out by reading the pdr register. note: when a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the ddr register for output, however, values of bits configured by the ddr register as inputs are changed because input values to the pins are written into the output latch. to avoid this situation, configure the pins by the ddr register as output after writing output data to the pdr register when configuring the bit used as input as outputs. ? operation as input port the pin is configured as an input by setting the corresponding bit of the ddr register to 0. when the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. when a data is written into the pdr register, the data is retained in the output latch of the pdr, but pin outputs are unaffected. reading the pdr register reads out the pin level (0 or 1). ? block diagram pdr (port data register) ddr (port direction register) pdr read pdr write ddr write ddr read direction latch output latch internal data bus standby control: stop, timebase timer mode and spl=1, or hardware standby mode standby control (spl=1) p-ch n-ch pin 29 MB90246a series (2) n-ch open-drain port port 6 is general-purpose i/o port having a combined function as resource input/output. each pin can be switched between resource and port bitwise. ? operation as output port when a data is written into the pdr register, the data is latched to the output latch of pdr. when the output latch value is set to 0, the output transistor is turned on and the pin status is put into an l level output, while writing 1 turns off the transistor and put the pin in a high-impedance status. if the output pin is pulled-up, setting output latch value to 1 puts the pin in the pull-up status. reading the pdr register returns the pin value (same as the output latch value in the pdr). note: execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather than the pin value, leaving output latch that is not manipulated unchanged. ? operation as input port setting corresponding bit of the pdr register to 1 turns off the output transistor and the pin is put into a high- impedance status. reading the pdr register returns the pin value (0 or 1). ? block diagram internal data bus ader (analog input enable register) pdr (port data register) ader read ader write ader latch pdr write pdr read output latch standby control: stop, timebase timer mode and spl=1, or hardware standby mode standby control (spl=1) to analog input pin output trigger rmw (read-modify-write type instruction) 30 MB90246a series (3) register configuration (continued) (pdr5) (pdr7) (pdr9) (vacancy) p17 p16 p15 p14 p13 p12 p11 p10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w (system reservation area) (pdr4) (pdr6) (pdr8) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p47 p46 p45 p44 p43 p42 p41 p40 p67 p66 p65 p64 p63 p62 p61 p60 p87 p86 p85 p84 p83 p82 pa5 pa4 pa3 pa2 pa1 pa0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w p57 p56 p55 p54 p53 p52 p51 p50 p76 p75 p74 p73 p72 p71 p70 p96 p95 p94 p93 p92 p91 p90 port 1 data register (pdr1) port 4 data register (pdr4) port 5 data register (pdr5) port 6 data register (pdr6) port 7 data register (pdr7) port 8 data register (pdr8) port 9 data register (pdr9) port a data register (pdra) address 000001 h address 000004 h address 000005 h address 000006 h address 000007 h address 000008 h address 000009 h address 00000a h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 8 ............ bit 15 bit 8 ............ bit 15 bit 8 ............ bit 15 bit 8 ............ p17 p16 p15 p14 p13 p12 p11 p10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w port 1 direction register (ddr1) address 000011 h (ddr5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p47 p46 p45 p44 p43 p42 p41 p40 r/w r/w r/w r/w r/w r/w r/w r/w port 4 direction register (ddr4) address 000014 h (ddr4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p57 p56 p55 p54 p53 p52 p51 p50 port 5 direction register (ddr5) address 000015 h r/w r/w r/w r/w r/w r/w r/w r/w (ddr7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p67 p66 p65 p64 p63 p62 p61 p60 r/w r/w r/w r/w r/w r/w r/w r/w analog input enable register (ader) address 000016 h bit 15 bit 8 ............ bit 15 bit 8 ............ bit 7 bit 0 ............. bit 7 bit 0 ............. bit 7 bit 0 ............. bit 7 bit 0 ............. bit 7 bit 0 ............. bit 7 bit 0 ............. (system reservation area) 31 MB90246a series (continued) (ader) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p76 p75 p74 p73 p72 p71 p70 port 7 direction register (ddr7) address 000017 h r/w r/w r/w r/w r/w r/w r/w (ddr9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p87 p86 p85 p84 p83 p82 r/w r/w r/w r/w r/w r/w port 8 direction register (ddr8) address 000018 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa5 pa4 pa3 pa2 pa1 pa0 r/w r/w r/w r/w r/w r/w port a direction register (ddra) address 00001a h (vacancy) (ddr8) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 p96 p95 p94 p93 p92 p91 p90 port 9 direction register (ddr9) address 000019 h r/w r/w r/w r/w r/w r/w r/w r/w r/w : readble and writable : unused ............ bit 15 bit 8 ............ bit 7 bit 0 ............. bit 15 bit 8 ............ bit 7 bit 0 ............. 32 MB90246a series 2. timebase timer the timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 2 13 /hclk, 2 15 /hclk, 2 17 /hclk, and 2 19 /hclk. the timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) register configuration (2) block diagram ? timebase timer control register (tbtc) resv bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w w r/w r/w (wdtc) address 0000a9 h tbie tbof tbr tbc1 tbc0 : readable and writable : write only : unused r/w w initial value 0xx00000 b : read only r : indeterminate : reserved bit x resv bit 7 bit 0 ............. . . . . . . to 8-bit pwm timer timebase timer counter divided-by-2 of hclk power-on reset start stop mode ckscr : mcs = 1 ? 0* 1 counter clear circuit interval timer selector clear tbof set tbof timebase timer control register (tbtc) timebase timer interrupt signal #25(19 h )* 2 : overflow : oscillation clock : switch machine clock from oscillation clock to pll clock : interrupt signal of hclk *1 *2 tbie tbr tbof tbc1 tbc0 to oscillation stabilization time selector of clock control block to watchdog timer of of of of 2 1 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 resv 33 MB90246a series 3. watchdog timer the watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the cpu when the counter is not cleared for a preset period of time. (1) register configuration (2) block diagram ? watchdog timer control register (wdtc) address 0000a8 h bit 15 bit 8 ponr stbr wrst erst srst wte wt1 wt0 (tbtc) r : read only w: write only x : indeterminate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrr rwww ............ initial value xxxxxxxx b hclk: oscillation clock ponr stbr wrst erst srst wte wt1 wt0 watchdog timer control register (wdtc) start sleep mode start hold status start stop mode clr and start watchdog timer overflow to internal reset generation circuit counter clear control circuit count clock selector 2-bit counter watchdog reset generation circuit clear divided-by-2 of hclk (timebase timer counter) 2 1 2 2 ... 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 clr 2 4 clr 34 MB90246a series 4. 8-bit pwm timer the 8-bit pwm timer is a re-load timer module that can generate a pulse wave with any period/duty ratio. it uses pulse output control according to timer operation for pwm (pulse width modulation) output. an appropriate external circuit allows the 8-bit pwm timer to operate as a d/a converter. the 8-bit pwm timer module consists of two 8-bit re-load registers used to specify h width and l width and of a down counter that is loaded alternately with those values and counts down. ? a pulse waveform with any period and duty ratio is generated. ? an output pulses duty ratio of 0.4 to 99.6 percent can be set. ? an appropriate external circuit allows this pwm timer to operate as a d/a converter. ? an interrupt request can be generated by counter underflow. ? the count clock can be selected from two types of timebase timer output. (1) register configuration ? pwm0 to 3 operating mode control register (pwm) ? pwm0 to 3 re-load register (prll, prlh) bit 15 bit 8 pen pcks poe pie puf resv (vacancy) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ bit 15 initial value 00000xx1 b 00000xx1 b 00000xx1 b 00000xx1 b address pwmc0 : 000034 h pwmc1 : 000038 h pwmc2 : 00003c h pwmc3 : 00002c h bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w address prlh0 : 000037 h prlh1 : 00003b h prlh2 : 00003f h prlh3 : 00002f h prll0 : 000036 h prll1 : 00003a h prll2 : 00003e h prll3 : 00002e h initial value xxxxxxx1 b xxxxxxx1 b xxxxxxx1 b xxxxxxx1 b xxxxxxx1 b xxxxxxx1 b xxxxxxx1 b xxxxxxx1 b r/w x resv : readable and writable : unused : indeterminate : reserved bit 35 MB90246a series (2) block diagram timerbase timer output (2 2 /hclk) timerbase timer output (2 11 /hclk) count clock selector down counter clear re-load re-load register l/h selector pwm re-load register (prll) temporary buffer pwm re-load register (prlh) pwm output latch output enable pin p85/pwm0 p86/pwm1 p87/pwm2 p93/int3/pwm3 #28(1c h ) #30(1e h ) #32(20 h ) #34(22 h ) interrupt request internal data bus pwm operationg mode control register (pwmc) pen pcks poe pie puf resv hclk : oscillation clock reverse clear 36 MB90246a series 5. 16-bit re-load timer the 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. for this timer, an underflow is defined as the timing of transition from the counter value of 0000 h to ffff h . according to this definition, an underflow occurs after [re-load register setting value + 1] counts. in operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent i/o service (ei 2 os). the MB90246a series has 3 channels of 16-bit re-load timers. (1) register configuration initial value xxxxxxxx b xxxxxxxx b xxxxxxxx b bit 7 bit 0 ? timer control status register 0, 1, 2 upper digits (tmcsr0, tmcsr1, tmcsr2: h) address tmcsr0 : 000041 h tmcsr1 : 000049 h tmcsr2 : 000051 h csl1 csl0 mod2 mod1 (tmcsr : l) r/wr/wr/wr/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. initial value ---- 0000 b bit 15 bit 8 ? timer control status register 0, 1, 2 lower digits (tmcsr0, tmcsr1, tmcsr2: l) address tmcsr0 : 000040 h tmcsr1 : 000048 h tmcsr2 : 000050 h oute mod0 (tmcsr : h) r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 initial value 00000000 b reld outl uf inte trg cnte ............. bit 3 bit 2 bit 1 bit 0 ? 16-bit timer register 0, 1 (tmr0, tmr1, tmr2) address bit 15 initial value xxxxxxxx b xxxxxxxx b xxxxxxxx b bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrrrrrrrrrrrrrr ? 16-bit re-load register 0, 1 (tmrl0,tmrl1) address bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wwwwwwwwwwwwwwww r/w : readable and writable r : read only w : write only : unused x : indeterminate tmr0 : 000042 h tmr1 : 00004a h tmr2 : 000052 h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tmrlr0 : 000044 h tmrlr1 : 00004c h tmrlr2 : 000054 h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 37 MB90246a series (2) block diagram internal data bus tmrlr0* 1 38 MB90246a series 6. 16-bit i/o timer the 16-bit i/o timer module consists of one 16-bit free-run timer, two input capture (icu) circuits, and four output comparators. this complex module allows two independent waveforms to be output on the basis of the 16-bit free-run timer. input pulse width and external clock periods can, therfore, be measured. the 16-bit i/o timer consists of: ? a 16-bit free-run timer; and ? two input captures (icu). ? block diagram internal data bus dedicated bus 16-bit free-run timer input capture (icu) 39 MB90246a series (1) 16-bit free-run timer the 16-bit free-run timer consists of a 16-bit up counter, a prescaler, and a control register. the value output from the timer counter is used as basic timer (base timer) for input capture (icu). ? a counter operation clock can be selected from four internal clocks. ? an interrupt request can be issued to the cpu by counter overflow. ? the extended intelligent i/o service (ei 2 os) can be activated. ? the 16-bit free-run timer counter is cleared to 0000 h by a reset or by clearing the timer (tccs: clk = 0). ? register configuration ? block diagram bit 15 bit 8 ? timer control status register (tccs) address 00006e h ivf resv (vacancy) bit 7 bit 6 bit 5 bit 4 initial value 00000000 b stop ivfe clr resv clk0 clk1 ............. bit 3 bit 2 bit 1 bit 0 ? timer data register (tcdt) bit 15 initial value bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t15 t14 t13 t12 t11 t10 t09 t08 t07 t06 t05 t04 t03 t02 t01 t00 r/w r/w r/w r/w r/w r/w r/w r/w address 00006d h 00006c h : readable and writable r/w : reserved bit resv 00000000 b 00000000 b timer data register (tcdt) of stop 16-bit free-run timer clk clr prescaler 2 timer control status register (tccs) resv ivf ivfe stop resv clr clk1 clk0 f count value output to input capture (icu) internal data bus free-run timer interrupt request #23 (17 h )* f of * : machine clock frequency : overflow : interrupt number 40 MB90246a series (2) input capture (icu) the input capture (icu) consists of a capture register corresponding to two 16-bit external input pins, a control register, and an edge detector. upon input of a trigger edge through an external input pin, the counter value of the 16-bit free-run timer is stored into the input capture register, and an interrupt request can be generated concurrently. ? a capture interrupt can be generated independently for each capture unit. ? the extended intelligent i/o service (ei 2 os) can be activated. ? a trigger edge direction can be selected from rising/falling/both edges. ? since two input capture units can be operated independent of each other, up to two events can be measured independently. ? the input capture function is suited for measurements of intervals (frequencies) and pulse-widths. ? register configuration ? block diagram bit 15 bit 8 ? input capture control status register (ics) icp0 icp1 (vacancy) bit 7 bit 6 bit 5 bit 4 initial value 00000000 b ice0 ice1 eg10 eg11 eg00 eg01 ............. bit 3 bit 2 bit 1 bit 0 ? input capture register (ipcp0, ipcp1) bit 15 initial value bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 r/w r/w r/w r/w r/w r/w r/w r/w address xxxxxxxx b xxxxxxxx b address ics0 : 000064 h ipcp0 : 000061 h ipcp1 : 000063 h ipcp0 : 000060 h ipcp1 : 000062 h r/w : readable and writable r : read only x : indeterminate 16-bit free-run timer internal data bus input capture register 1 (ipcp1) input capture register 0 (ipcp0) edge detection circuit pin pin p71/asr1 p70/asr0 icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 #17 (11 h ) #15 (of h ) input capture control status register(ics) input capture interrupt request (icu) *: interrupt number 41 MB90246a series 7. simple i/o serial interface the 8/16-bit simple i/o serial interface transfers data synchronously with a clock. ? communications direction: concurrent processing of transmission (whether data is to be sent or received must be judged by the user.) ? transfer mode: clock synchronization function (only data are transferred.) ? transfer rate:dc to f /2 ( f : machine clock. frequencies of up to 8 mhz are available when the machine clock is rated at 16 mhz.) ? shift clock: a machine clock division clock is used as the shift clock. (one of four division ratios can be selected.). a shift clock is output only during data transfer. ? data transfer format: msb first can be selected. 8 or 16 bits can be selected as data length. only data are transferred. ? interrupt request: an interrupt request is issued upon termination of transfer. ? inter-cpu connection: only 1:1 (bidirectional communication) (1) register configuration ssr1 : 000021 h ssr2 : 000025 h bit 15 bit 8 ? serial control status register 1, 2 (scr) ocke stop (ssr) bit 7 bit 6 bit 5 bit 4 initial value 10000000 b sie soe wbs sir smd0 smd1 ............. bit 3 bit 2 bit 1 bit 0 ? serial data register 1, 2 (sdr) bit 15 initial value bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 r/w r/w r/w r/w r/w r/w r/w r/w address -------1 b address scr0 : 000020 h scr1 : 000024 h sdr1h : 000023 h sdr2h : 000027 h sdr1l : 000022 h sdr2l : 000026 h r/w : readable and writable r : read only : unused x : indeterminate initial value xxxxxxxx b xxxxxxxx b (scr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 busy address bit 7 bit 0 ............. r ? serial status register 1, 2 (ssr) 42 MB90246a series (2) block diagram internal data bus pin pa0/sid1 pa3/sid2 stop soe pin pin pa1/sod1 pa4/sod2 pa2/sck1 pa5/sck2 serial data register (sdr) sdrh sdrl control circuit shift clock counter 2 ocke sie wbs smd1 smd0 sir busy serial control status register (scr) serial status register (ssr) f * : machine clock frequency : interrupt number #35 (23 h )* #18 (12 h )* serial i/o interrupt request 43 MB90246a series 8. uart uart0 is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). in addition to the normal duplex communication function (normal mode), uart0 has a master-slave type communication function (multi-processor mode). ? data buffer: full-duplex double buffer ? transfer mode:clock synchronized (with start and stop bit) clock asynchronized (start-stop synchronization system) ? baud rate: with dedicated baud rate generator, selectable from 12 types external clock input possible internal clock (a clock supplied from 16-bit re-load timer 2 can be used.) ? data length: 7 bit to 9 bit selective (with a parity bit) 6 bit to 8 bit selective (without a parity bit) ? signal format: nrz (non return to zero) system ? reception error detection: framing error overrun error parity error (not available in multi-processor mode) ? interrupt request: receive interrupt (receive complete, receive error detection) receive interrupt (transmit complete) transmit/receive conforms to extended intelligent i/o service (ei 2 os) ? master/slave type communication function: 1 (master) to n (slave) communication possible (multi-processor mode) (1) register configuration ? status register (usr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 000029 h initial value 00010000 b bit 7 bit 0 ............. r/w r/w r/w r/w r/w w r/w r/w address 000028 h initial value 00000100 b bit 15 bit 8 ............ bch rc3 rc2 rc1 rc0 bch0 p d8 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 00002b h initial value 00000000 b (uidr/uodr) bit 7 bit 0 ............. ? input data register (uidr) d7 d6 d5 d4 d3 d1 d0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address 00002a h initial value xxxxxxxx b (urd) bit 15 bit 9 ..... bit 8 d8 ? output data register (uodr) address 00002a h initial value xxxxxxxx b r/w : readable and writable r : read only w : write only x : indeterminate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 9 ..... bit 8 pen sbl mc1 mc0 smde rfc scke soe (usr) r/w r/w r/w r/w r/w r/w r/w r/w d2 rrrrr rr rr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdrf oref pe tdre rie bch0 rbf tbf (umc) rrrrr/wr/wrr ? mode control register (umc) d7 d6 d5 d4 d3 d1 d0 (urd) d8 d2 wwwww ww ww ? rate and data register (urd) 44 MB90246a series (2) block diagram clock selector dedicated baud rate generator 16-bit re-load timer 2 pin p96/sck0 pin p94/sid0 receive condition decision circuit umc register usr register urd register receive clock receive control circuit start bit detection circuit receive bit counter receive parity counter shift register for reception uidr uodr transmit clock transmit control circuit transmit start circuit transmit bit counter transmit parity counter shift register for transmission receive interrupt signal #39 (27 h )* transmit interrupt signal #37 (25 h )* pin p95/sod0 start transmission to ei 2 os reception error generation signal (to cpu) internal data bus pen sbl mc1 mc0 smde rfc scke soe rdrf orfe pe tdre rie tie rbf tbf bch rc2 rc1 rc0 bch0 p d8 * : interrupt number control bus reception complete rc3 45 MB90246a series 9. dtp/external interrupt circuit the dtp (data transfer peripheral)/external interrupt circuit is located between peripheral equipment connected externally and the f 2 mc-16f cpu and transmit interrupt requests or data transfer requests generated by peripheral equipment to the cpu, generates external interrupt request and starts the extended intelligent i/o service (ei 2 os). (1) register configuration r/w: readable and writable : unused resv : reserved bit ? dtp/interrupt factor register (eirr) address 000031 h bit 7 bit 0 resv resv resv resv er3 er2 er1 er0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (enir) initial value - - - - 0000 b r/wr/wr/wr/w address 000030 h bit 15 bit 8 resv resv resv resv en3 en2 en1 en0 (eirr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w r/w r/w r/w initial value - - - - 0000 b address 000032 h bit 15 bit 8 lb3 la3 lb2 la2 lb1 la1 lb0 la0 (vacancy) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b ? dtp/interrupt enable register (enir) ? request level setting register (elvr) 46 MB90246a series (2) block diagram #21 (15 h )* #19 (13 h )* #13 (0d h )* #11 (0b h )* pin request level setting register (elvr) p93/int3/ pwm3 pin p92/int2/atg pin p91/int1 pin p90/int0 lb3 la3 lb2 la2 lb1 la1 lb0 la0 level edge selector 3 level edge selector 1 level edge selector 2 level edge selector 0 dtp/external interrupt input detection circuit dtp/interrupt factor register (eirr) dtp/interrupt enable register (enir) *: interrupt signal i n t e r n a l d a t a b u s interrupt request signal resv resv resv resv er3 er2 er1 er0 resv resv resv resv en3 en2 en1 en0 22 2 2 47 MB90246a series 10. delayed interrupt generation module the delayed interrupt generation module generates interrupts for switching tasks for development on a real- time operating system (realos series). the module can be used to generate softwarewise generates hardware interrupt requests to the cpu and cancel the interrupts. this module does not conform to the extended intelligent i/o service (ei 2 os). (1) register configuration (2) block diagram ? delayed interrupt factor generation/cancellation register (dirr) address 00009f h bit 7 bit 0 r0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (system reservation area) r/w initial value -------0 b r/w: readable and writable : unused delayed interrupt factor generation/ cancellation register (dirr) *: interrupt signal s factor r latch r0 internal data bus interrupt request signal #42 (2a h )* 48 MB90246a series 11. 8/10-bit a/d converter the 8/10-bit a/d converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (a/d conversion) and has the following features. ? minimum conversion time: 6.13 m s (at machine clock of 16 mhz, including sampling time) ? minimum sampling time: 3.75 m s (at machine clock of 16 mhz) ? conversion time: the sampling time can be set arbitrarily. serial to parallel converter with a sample hold circuit ? conversion method ? resolution: 10-bit or 8-bit selective ? analog input pins: selectable from eight channels by software single conversion mode: single conversion for the specified channel scan conversion mode: scan conversions for maximum of four channel ? interrupt requests can be generated and the extended intelligent i/o service (ei 2 os) can be started after the end of a/d conversion. ? starting factors for conversion: selected from software activation, 16-bit re-load timer 1 output (rising edge), and external trigger (falling edge). ? a data buffer that covers four channels is supported. the results of conversion are stored into the data buffer. 49 MB90246a series (1) register configuration ? a/d control status register upper digits (adcsh) address 000071 h bit 7 bit 0 acs2 acs1 acs0 creg scan bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (adcsl) r/w r/w r/w r/w r/w address 000070 h bit 15 bit 8 busy int inte sts1 sts0 star resv (adcsh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w ............ ? a/d control status register lower digits (adcsl) address ? a/d data register 0 to 3 (adth, adtl) d9d8d7d6d5d4d3d2d1d0 rrr rrr * * rrrrrrrr initial value 000 - 0000 b initial value - 000 - - 00 b initial value ------ b xxxxxxxx b ** bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 adth0 : 000075 h adth1 : 000077 h adth2 : 000079 h adth3 : 00007b h adtl0 : 000074 h adtl1 : 000076 h adtl2 : 000078 h adtl3 : 00007a h address 000073 h 000072 h smp3 smp2 smp1 smp0 cv03 cv02 cv01 cv00 cv13 cv12 cv11 cv10 cv23 cv22 cv21 cv20 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ? conversion time setting register (adct) initial value xxxxxxxx b xxxxxxxx b ? analog input enable register (ader) address 000016 h bit 15 bit 8 ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 (ddr7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ initial value 11111111 b r/w: readable and writable r : read only :unused x : indeterminate * : the creg bit value of adcsh makes different storage styles. resv : reserved bit 50 MB90246a series (2) block diagram conversion time setting register (adct) sample hold circuit smp3 2 3 4 4 4 4 smp2 smp1 smp0 cv03 cv02 cv01 cv00 cv13 cv12 cv11 cv10 cv23 cv22 cv21 cv20 acs2 acs1 acs0 creg scan busy int inte sts1 sts0 star resv f to p92/int2/atg analog channel selector a/d converter control circuit clock selector a/d data register 0 to 3 adth0 to adth3, adtl0 to adtl3 register selection internal data bus a/d control status register (adcs) avrh avrl av cc av ss f : machine clock frequency to : 16-bit re-load timer channel 1 output p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 interrupt request #33 (21 h ) 51 MB90246a series 12. 8-bit d/a converter the 8-bit d/a converter, which is based on the r-2r system, supports 8-bit resolution mode. it contains two channels each of which can be controlled in terms of output by the d/a control register. (1) register configuration ? d/a control register 0 (dacr0) ? d/a control register 1 (dacr1) ? d/a control register 2 (dacr2) ? d/a data register 0 (dadr0) ? d/a data register 1 (dadr1) ? d/a data register 2 (dadr2) initial value -------0 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 00005b h (dadr0) bit 7 bit 0 ............. dae0 r/w initial value -------0 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 00005d h (dadr1) bit 7 bit 0 ............. dae1 r/w initial value -------0 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 00005f h (dadr2) bit 7 bit 0 ............. dae2 r/w initial value xxxxxxxx b address 00005a h (dacr0) da07 da06 da05 da04 da03 da02 da01 da00 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b address 00005c h r/w r/w r/w r/w r/w r/w r/w r/w (dacr1) da17 da16 da15 da14 da13 da12 da11 da10 initial value xxxxxxxx b address 00005e h (dacr2) da27 da26 da25 da24 da23 da22 da21 da20 r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ r/w : readable and writable :unused x : indeterminate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ 52 MB90246a series (2) block diagram da 7 standby control da 6da 5da 4da 3da 2da 1da 0 dae d/a data register (dadr0) 53 MB90246a series 13. dsp interface for the iir filter the dsp interface for the iir filter is a unit which covers product addition ( s bi yj + s am xn) by hardware. this interface allows iir filter calculation to be performed readily and in a high speed. the dsp interface for the iir filter has the following features. ? coefficients a and b, and variables x and y have 16-bit length, and four banks are supported. ? (1 to 4) + (1 to 4) product terms can be selected. ? data can be rounded and clipped in units of 10 or 12 bits. ? with two or more concatenated banks used, the results of an operation can be transferred to the subsequent bank register. ? operation time: ((m + n + 1) b + 1)/ f m s(m, n = number of product terms, b = number of banks, f : machine clock) (1) register configuration ? product addition control status register upper digits (mcsr:h) initial value - xxxxxxx b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 000081 h (mcsr:l) bit 7 bit 0 ............. weyweny wenx n1 n0 m1 m0 r/wr/w r/w r/w r/w r/w r/w ? product addition control status register lower digits (mcsr:l) initial value 00000000 b address 000082 h (mccr:h) ovf cntd cntc cntb cdrd cdrc cdrb cdra r/w r/w r/w r/w r/w r/w r/w r/w initial value xxx0xxx0 b address 000080 h (mcsr:h) rnd clp div bf bnk1 bnk0 trg mae r/w r/w r/w r r/w r/w w r/w initial value ------00 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 000083 h (mccr:l) bit 7 bit 0 ............. resv resv r/wr/w initial value xxxxxxxx b address mdorh : 000088 h d23 d22 d21 d20 d19 d18 d17 d16 d24 d25 d26 d27 d28 d29 d30 d31 bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 sss s sd34d33d32 rrr r rrrr d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 d10 d11 d12 d13 d14 d15 rrr r rrrr r r r r r r r r rrr r rrrr r r r r r r r r xxxxxxxx xxxxxxxx b mdorm : 000086 h mdorl : 000084 h xxxxxxxx xxxxxxxx b ? product addition control register upper digits (mccr:h) ? product addition control register lower digits (mccr:l) ? product addition output register (mdorl, m, h) r/w: readable and writable r : read only w : write only : unused x : indeterminate resv : reserved bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ 54 MB90246a series (2) block diagram internal data bus 4 register selection bank selection 3 4 3 2 register selection register selection transfer data selector transfer data selector coefficient register coefficient register input data register input data register a0 to a3 b0 to b3 x0 to x3 y0 to y3 coefficient register selector bank/register selector input data selector product addition unit product adder right shift and clip product addition control register (mccr) product addition output register m product addition output register l product addition output register h (mdorl) (mdorm) product addition control status register (mcsr) (mdorh) ovf cntd cntc cntb cdrd cdrc cdrb cdra wey weny wenx n1 n0 m1 m0 rnd clp div bf bnk1 bnk0 trg mae 55 MB90246a series 14. low-power consumption (stand-by) mode the f 2 mc-16f has the following cpu operating mode configured by selection of an clock operation control. ? stand-by mode the hardware stand-by mode is a mode for reducing power consumption by stopping clock supply to the cpu by the low-power consumption control circuit, and stopping oscillation clock (stop mode, hardware standby mode). gear function contributes to the low-power dissipation by providing options of divide-by-2, 4, or 16 external clock frequencies, whichiare usually derived from non-divided frequencies. (1) register configuration ? standby control register (stbyc) address 0000a0 h bit 15 bit 8 stp slp spl rst osc1 osc0 clk1 clk0 (vacancy) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w w r/w r/w r/w r/w r/w r/w ............ r/w : readable and writable w : write only x : indeterminate initial value 0001xxxx b 56 MB90246a series (2) block diagram pin hi-z control low-power consumption mode control register (stbyc) internal reset cpu clock stop and sleep signal stop signal main clock clock selector cancellation of oscillation stabilization time machine clock cancellation of interrupt cancellation of reset rst hst standby control circuit rst internal reset generation circuit pin pin x0 pin x0 pin stp slp spl rst osc1 osc0 clk1 clk0 pin high-impedance control circuit cpu clock control circuit peripheral clock control circuit divided -by-2 divided -by-2 14 divided -by-2 divided -by-2 divided -by-2 peripheral clock timebase timer system clock generation circuit clock generation block oscillation stabilization time selector 2 2 2 divided -by-2 divided -by-4 ddc: direct duty control oscillation clock ddc 57 MB90246a series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: av cc , avrh, avrl, dvrh and dvrl shall never exceed v cc . dvrl shall never exceed dvrh. avrl shall never exceed avrh. *2: v i and v o shall never exceed v cc + 0.3 v. *3: the maximum output current is a peak value for a corresponding pin. *4: average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: total average current is an average current value observed for a 100 ms period for all corresponding pins. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc v ss C 0.3 v ss + 7.0 v *1 avrh, avrl v ss C 0.3 v ss + 7.0 v *1 dvrh, dvrl v ss C 0.3 v ss + 7.0 v *1 input voltage v i v ss C 0.3 v cc + 0.3 v *2 output voltage v o v ss C 0.3 v cc + 0.3 v *2 l level maximum output current i ol ? 10 ma *3 l level average output current i olav ? 4ma*4 l level total average output current s i olav ? 50 ma *5 h level maximum output current i oh ? C10 ma *3 h level average output current i ohav ? C4 ma *4 h level total average output current s i ohav ? C48 ma *5 power consumption p d ? 600 mw operating temperature t a C30 +70 c storage temperature tstg C55 +150 c 58 MB90246a series 2. recommended operating conditions (av ss = v ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 4.5 5.5 v normal operation v cc 2.0 5.5 v retains ram data at the time of operation stop operating temperature t a C30 +70 c external bus mode 59 MB90246a series 3. dc characteristics (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih cmos input pin 0.7 v cc v cc + 0.3 v v ih2 ttl input pin v cc = 5.0 v 10% 2.2 v cc + 0.3 v v ih1s hysteresis input pin 0.8 v cc v cc + 0.3 v v ihm md0 to md2 v cc C 0.3 v cc + 0.3 v l level input voltage v il1 cmos input pin v cc C 0.3 0.3 v cc v v il2 ttl input pin v cc = 5.0 v 10% v cc C 0.3 0.8 v v il1s hysteresis input pin v cc C 0.3 0.2 v cc v v ilm md0 to md2 v cc C 0.3 v cc + 0.3 v h level output voltage v oh all ports other than p60 to p67 v cc = 4.5 v i oh = C4.0 ma v cc C 0.5 v l level output voltage v ol all output pins v cc = 4.5 v i ol = 4.0 ma 0.4v open-drain output leakage current i leak p60 to p67 0.1 10 m a h level input current i ih1 cmos input pins other than rst v cc = 5.5 v v ih = 0.7 v cc C10 m a i ih2 ttl input pin v cc = 5.5 v v ih = 2.2 v cc C10 m a i ih3 hysteresis input pin v cc = 5.5 v v ih = 0.8 v cc C10 m a l level input current i il1 cmos input pins other than rst v cc = 5.5 v v il = 0.3 v cc 10 m a i il2 ttl input pin v cc = 5.5 v v il = 0.8 v 10 m a i il3 hysteresis input pin v cc = 5.5 v v il = 0.2 v cc 10 m a pull-up resistance rrst 22 110 k w 60 MB90246a series (continued) (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) parameter symbol pin name condition value unit remarks min. typ. max. power supply current i cc v cc internal operation at 16 mhz v cc = 5.0 v 10% normal operation 80 100 ma i ccs internal operation at 16 mhz v cc = 5.0 v 10% in sleep mode 3050ma i cch t a = +25 c v cc = 4.5 v to 5.5 v in stop mode and hardware standby mode 0.110 m a input capacitance c in other than av cc , av ss , v cc , v ss 10pf 61 MB90246a series 4. ac characteristics (1) reset, hardware standby input timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : for t cyc (cycle time (machine cycle)), see paragraph (4), "clock output timing." note: upon hardware standby input, divide-by-32 is selected as the machine cycle. parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 5 t cyc * ns hardware standby input time t hstl hst 5 t cyc * ns 0.2 v cc t rstl , t hstl rst hst 0.2 v cc ? measurement conditions for ac ratings pin c l c l is a load capacitance connected to a pin under test. capacitors of c l = 30 pf should be connected to clk pin, while c l of 80 pf is connected to address bus (a23 to a00) and data bus (d15 to d00), rd , wrh and wrl pins. 62 MB90246a series (2) specification for power-on reset (av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : v cc must be kept lower than 0.2 v before power-on. notes: ? the above ratings are values for causing a power-on reset. ? when hst is set to l, apply power according to this table to cause a power-on reset irrespective of whether or not a power-on reset is required. ? for built-in resources in the device, re-apply power to the resources to cause a power-on reset. parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc 30ms* power supply cut-off time t off v cc 1ms due to repeated operations v cc t off 0.2 v 4.5 v 0.2 v 0.2 v t r ram data retained v ss sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. main power supply voltage sub power supply voltage it is recommended to keep the rising speed of the supply voltage at 50 mv/ms. v cc 63 MB90246a series (3) clock timings ? operation at 5.0 v 10% (av ss = v ss = 0.0 v, t a = C30 c to +70 c) parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f c x0, x1 v cc = 5.0 v 10% 16 32 mhz clock cycle time t c x0, x1 1/fc ns input clock pulse width p wh , p wl x0 10 ns recommended duty ratio of 30% to 70% input clock rising/ falling time t cr , t cf x0 v cc = 5.0 v 10% 11 ns maximum value = t cr + t cf ?clock timings p wh 0.3 v cc 0.7 v cc 0.7 v cc 0.7 v cc 0.3 v cc p wl t cf t cr t c ? relationship between clock frequency and power supply voltage 0 16 (mhz) power supply voltage v cc 5.5 4.5 (v) normal operation range (t a = C30 c to +70 c) clock frequency f c 32 64 MB90246a series (4) clock output timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) *1: for t c (clock cycle time), refer to (3) clock timings. *2: this case is applied when the lowest speed (1/16) is selected by the clock gear function with the clock frequency (f c ) set at 16 mhz. parameter symbol pin name condition value unit remarks min. max. cycle time (machine cycle) t cyc clk 2 t c * 1 32t c * 1 * 2 ns clk - ? clk t chcl clk v cc = 5.0 v 10% 1 t cyc /2 C 20 1 t cyc /2 + 20 ns 2.4 v 0.8 v t cyc t chcl 2.4 v clk 65 MB90246a series (3) bus read timing (av cc = v cc = 2.7 v to 5.5 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) n: stands for the number of wait cycles. with no wait, n is set at 0. (the number of wait cycles depends on an automatic wait and external rdy.) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. parameter symbol pin name condition value unit remarks min. max. effective address ? rd time t avrl a00 to a23 v cc = 5.0 v 10% 1 t cyc */2 C 20 ns effective address ? effective data input t avdv d15 to d00 (n + 1.5) 1 t cyc * C 40 ns rd pulse width t rlrh rd (n + 1) 1 t cyc * C 25 ns rd ? effective data input t rldv d15 to d00 v cc = 5.0 v 10% (n + 1) 1 t cyc* * C 30 ns rd - ? data hold time t rhdx d15 to d00 0ns rd - ? address effective time t rhax a00 to a23 1 t cyc */2 C 20 ns effective address ? clk - time t avch clk, a00 to a23 1 t cyc */2 C 25 ns rd ? clk - time t rlcl rd , clk 1 t cyc */2 C 25 ns clk rd a00 to a23 d00 to d15 t avch t rlcl 2.4 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v t avrl t avdv t rldv t rhax t rhdx t rlrh 0.8 v 2.4 v 0.8 v 2.2 v 0.8 v 2.2 v 0.8 v 66 MB90246a series (4) bus write timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) n: stands for the number of wait cycles. with no wait, n is set at 0. (the number of wait cycles depends on an automatic wait and external rdy.) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. parameter symbol pin name condition value unit remarks min. max. effective address ? wrl , wrh time t avwl a00 to a23 v cc = 5.0 v 10% 1 t cyc */ 2 C 20 ns wrl , wrh pulse width t wlwh wrl , wrh (n + 1) 1 t cyc* * C 25 ns write data ? wrl , wrh - time t dvwh d15 to d00 (n + 1) 1 t cyc * C 40 ns wrl , wrh - ? data hold time t whdx d15 to d00 v cc = 5.0 v 10% 1 t cyc */ 2 C 20 ns wrl , wrh - ? address effective time t whax a00 to a23 1 t cyc */ 2 C 20 ns wrl , wrh ? clk time t wlcl wrl , clk 1 t cyc */ 2 C 25 ns clk wrl , wrh a00 to a23 d00 to d15 t wlcl t avwl t wlwh 2.4 v 0.2 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v write data t whax t dvwh t whdx 2.4 v 0.8 v 2.4 v 0.2 v 67 MB90246a series (5) ready input timing ? clk signal standards (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) n: stands for the number of wait cycles. with no wait, n is set at 0. (the number of wait cycles depends on an automatic wait and external rdy.) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. note: use the automatic ready function when the setup time for the rising edge of the rdy signal is not sufficient. parameter symbol pin name condition value unit remarks min. max. rd /wrh /wrl ? rdy time t ryhs rd /wrh / wrl , rdy 0 n 1 t cyc * + 15 ns rdy setup time (in diallocating) t rhdv rdy v cc = 5.0 v 10% 30 ns rdy hold time t ryhh rdy 0 ns clk rd /wrh /wrl rdy (wait not inserted) rdy (wait inserted) a00 to a23 t rhdv 0.8 v t ryhh 2.2 v 2.2 v 0.8 v 0.8 v 2.2 v 2.2 v ? ready input timing (clk signal standards) t ryh t ryhh 68 MB90246a series ?rd /wrh /wrl signal standards (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) n: stands for the number of wait cycles. with no wait, n is set at 0. (the number of wait cycles depends on an automatic wait and external rdy.) m: stands for the number of rdy wait cycles. with no wait, m is set at 0. *1: use the automatic ready function when the setup time is not sufficient. *2: if the pulse width has exceeded the maximum value, the wait period may be extended beyond the specified number of cycles by one cycle. *3: for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. parameter symbol pin name condition value unit remarks min. max. rd /wrh /wrl ? rdy time t ryhs rd /wrh / wrl , rdy 0 n 1 t cyc * 3 + 15* 1 ns rdy pulse width t rypw rdy v cc = 5.0 v 10% 1/2 t cyc * 3 + 20 (m + 1) 1 t cyc * 2, * 3 ns rdy - ? rd - t rhdv rd /wrh / wrl , rdy 1 t cyc * 3 C 15 2 t cyc * 3 C 25 ns rd /wrh /wrl rdy (wait not inserted) rdy (wait inserted) a00 to a23 t rhdv 0.8 v t ryhs 2.2 v 0.8 v 2.4 v ? ready input timing (rd /wrh /wrl signal standards) 2.2 v t rypw 2.2 v 0.8 v 69 MB90246a series (8) hold timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. note: more than 1 machine cycle is needed before hak changes after hrq pin is fetched. (9) uart timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. notes: ? these are ac ratings in the clk synchronous mode. ?c l is the load capacitor value connected to pins while testing. parameter symbol pin name condition value unit remarks min. max. pins in floating status ? hak time t xhal hak v cc = 5.0 v 10% 30 1 t cyc *ns hak - ? pin valid time t hahv hak 1 t cyc *2 t cyc *ns parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0 8 t cyc *ns internal shift clock mode c l = 80 pf for an output pin sck ? sod delay time t slov sck0, sod0 v cc = 5.0 v 10% C80 80 ns valid sid ? sck - t ivsh sck0, sid0 100 ns sck - ? valid sid hold time t shix sck0, sid0 60 ns serial clock h pulse width t shsl sck0 4 t cyc *ns external shift clock mode c l = 80 pf for an output pin serial clock l pulse width t slsh sck0 4 t cyc *ns sck ? sod delay time t slov sck0, sid0 v cc = 5.0 v 10% 150 ns valid sid ? sck - t ivsh 60ns sck - ? valid sid hold time t shix sck0, sid0 60 ns pins hak high impedance t xhal t hahv 0.8 v 2.4 v hrq 70 MB90246a series ? internal shift clock mode ? external shift clock mode sck0 2.4 v 0.8 v sod0 sid0 sck0 sod0 sid0 0.8 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t scyc t ivsh t shix t slov t slsh t shsl t ivsh t shix t slov 71 MB90246a series (10) timer input timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. (11) timer output timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t tiwh , t tiwl asr0, asr1, tin0 to tin2 4 t cyc *ns parameter symbol pin name condition value unit remarks min. max. clk - ? tot transition time t to tot0 to tot2, pwm0 to pwm3 v cc = 5.0 v 10% 40 ns t tiwh 0.8 v cc 0.2 v cc t tiwl 0.8 v cc 0.2 v cc asr0, asr1 tin0 to tin2 clk t to 2.4 v tot 2.4 v 0.8 v 72 MB90246a series (12) i/o simple serial timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. note: c l is the load capacitor value connected to pins while testing. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck1, sck2 2 t cyc *ns internal shift clock mode c l = 80 pf for an output pin sck ? sod delay time t slov sck1, sod1, sck2, sod2, 1 t cyc */2 ns valid sid ? sck - t ivsh sck1, sid1, sck2, sid2, 1 t cyc *ns sck - ? valid sid hold time t shix sck1, sid1, sck2, sid2, 1 t cyc *ns sck1, sck2 t scyc 0.8 v 2.4 v ? internal shift clock mode 0.8 v t slov t ivsh t shix 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sod1, sod2 sid1, sid2 73 MB90246a series (13) trigger input timing (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) * : for t cyc (cycle time (machine cycle)), see paragraph (4), clock output timing. parameter symbol pin name condition value unit remarks min. max. input pulse width t trgh , t trgl atg , int0 to int3 5 t cyc *ns t trgh 0.8 v cc 0.2 v cc t trgl 0.8 v cc 0.2 v cc atg int0 to int3 74 MB90246a series 5. a/d converter electrical characteristics (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) *1: glossary for conversion time *2: ias and irs signify currents when the a/d converter does not operate and when the cpu is out of service, respectively. parameter symbol pin name condition value unit min. typ. max. resolution 8, 10 10 bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an7 avrl C 1.0 lsb avrl + 1.0 lsb avrl + 3.0 lsb mv full-scale transition voltage v fst an0 to an7 avrh C 4.0 lsb avrh C 1.0 lsb avrh + 1.0 lsb mv conversion time* 1 use the a/d data register for setup. v cc = 5.0 v 10% 1.25 m s sampling period 560 ns conversion period a 125 ns conversion period b 125 ns conversion period c 250 ns analog port input current i ain an0 to an7 0.1 3 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrh C avrl 2.7 avrl + 2.7 av cc v avrl 0 avrh C 2.7 v power supply current i a av cc 15 20 ma i as * 2 av cc supply current when the cpu stops (av cc = 5.5 v) 5 m a reference voltage supply current i r avrh 0.7 2 m a i rs * 2 avrh supply current when the cpu stops (av cc = 5.5 v) 5 m a offset between channels an0 to an7 4 lsb 3 conversion time sampling period conversion period a conversion period b conversion period c 2 t cyc * 1 t cyc * end of conversion a/d activation adcs bit 1: sets star * : for t cyc , see n electrical characteristics, 4, ac characteristics, cycle time (machine cycle) in paragraph (4), clock output timing. adcs bit 6: int h (interrupt occurred to cpu) 75 MB90246a series 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter with 10 bits supported, an analog voltage can be divided into 2 10 parts. linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error: the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, linearity error, differential linearity error and error caused by noise. 11 1111 1111 11 1111 1110 ? ? ? ? ? ? ? ? ? ? ? 00 0000 0010 00 0000 0001 00 0000 0000 v ot v nt v (n + 1)t v fst (1 lsb n + v ot ) linearity error 1 lsb = = [lsb] = C 1 lsb [lsb] 1022 v fst C v ot linearity error 1 lsb v nt C (1 lsb n + v ot ) differential linearity error 1 lsb v ( n+1 )t C v nt digital output 76 MB90246a series 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions. output impedance values of the external circuit of 300 w or lower are recommended. when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling time = 0.56 m s @machine clock of 16 mhz). ?error the smaller the | avrh C avrl |, the greater the error would become relatively. 8. 8-bit d/a converter electrical characteristics (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C30 c to +70 c) parameter symbol pin name condition value unit min. typ. max. resolution 8 8bit differential linearity error 0.9 lsb absolute accuracy v cc = dvrh = 5.0 v, dvrl = 0.0 v 1.2% conversion time load capacitance: 20 pf 1020 m s analog power supply voltage dvrh v ss + 2.0 v cc v dvrl dvrh C dvrl 2.0 v v ss v cc C 2.0 v reference voltage supply current i d dvrh during conversion 1.0 1.5 ma i dh dvrh when the cpu is stopped 10 m a analog output impedance 28k w ? block diagram of analog input circuit model note: listed values must be considered as standards. comparator analog input pin r on1 : approx. 300 w r on2 : approx. 150 w c 0 : approx. 60 pf c 1 : approx. 4 pf r on1 r on2 c 0 c 1 comparator comparator 3 77 MB90246a series n example characteristics (3) power supply current (1) h level output voltage (2) l level output voltage 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v cc C v oh v cc = 5.0 v v oh C i oh t a = +25 c i oh (ma) C2 C4 C6 C8 v ol (v) v ol C i ol 80 70 60 50 40 30 20 10 0 v cc (v) 4.0 i cc (ma) i cc C v cc 0 v cc = 5.0 v 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 t a = +25 c i ol (ma) 2468 0 4.5 5.0 5.5 6.0 16 mhz 13 mhz 10 mhz 8 mhz 4 mhz 2 mhz 25 20 15 10 5 0 v cc (v) 4.0 i ccs (ma) i ccs C v cc 4.5 5.0 5.5 6.0 16 mhz 13 mhz 10 mhz 8 mhz 4 mhz 2 mhz internal operating frequency internal operating frequency 78 MB90246a series n instructions (421 instructions) table 1 description of items in instruction list item description mnemonic english upper case and symbol: described directly in assembler code. english lower case: converted in assembler code. number of letters after english lower case: describes bit width in code. # describes number of bytes. ~ describes number of cycles. for other letters in other items, refer to table 4. b describes correction value for calculating number of actual states. number of actual states is calculated by adding value in the ~section. operation describes operation of instructions. lh describes a special operation to 15 bits to 08 bits of the accumulator. z : transfer 0. x : sign-extend and transfer. C : no transmission ah describes a special operation to the upper 16-bit of the accumulator. * : transmit from al to ah. C : no transfer. z : transfer 00 h to ah. x : sign-extend al and transfer 00 h or ff h to ah. i describes status of i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry) flags. * : changes after execution of instruction. C : no changes. s : set after execution of instruction. r : reset after execution of instruction. s t n z v c rmw describes whether or not the instruction is a read-modify-write type (a data is read out from memory etc. in single cycle, and the result is written into memory etc.). * : read-modify-write instruction C : not read-modify-write instruction note: not used to addresses having different functions for reading and writing operations. 79 MB90246a series table 2 description of symbols in instruction table (continued) item description a 32-bit accumlator the bit length is dependent on the instructions to be used. byte : lower 8-bit of al word :16-bit of al long : al: 32-bit of ah ah upper 16-bit of a al lower 16-bit of a sp stack pointer (usp or ssp) pc program counter spcu stack pointer upper limited register spcl stack pointer lower limited register pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb brg2 dtb, adb, ssb, usb, dpr ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 specify shortened direct address. specify direct address. specify physical direct address. bit0 to bit15 of addr24 bit16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) #imm4 #imm8 #imm16 #imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data calculated by sign-extending an 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value vct4 vct8 vector number (0 to 15) vector number (0 to 255) 80 MB90246a series (continued) table 3 effective address field note: number of bytes for address extension corresponds to + in the # (number of bytes) part in the instruction table. item description ( )b bit address rel ear eam specify pc relative branch. specify effective address (code 00 to 07). specify effective address (code 08 to 1f). rlst register allocation code symbol address type number of bytes in address extension block* 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct "ea" corresponds to byte, word, and long word from left respectively. 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2 81 MB90246a series table 4 number of execution cycles in addressing modes note: (a) is used for ~ (number of cycles) and b (correction value) in instruction table. table 5 correction value for number of cycles for calculating actual number of cycles notes: ? (b), (c), (d) is used for ~ (number of cycles) and b (correction value) in instruction table. code operand (a)* number of execution cycles for addressing modes 00 to 07 ri rwi rli listed in instruction table 08 to 0b @rwj 1 0c to 0f @rwj + 4 10 to 17 @rwi + disp8 1 18 to 1b @rwj + disp16 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 2 2 2 1 operand (b)* (c)* (d)* byte word long internal register +0 +0 +0 internal ram even address internal ram odd address +0 +0 +0 +1 +0 +2 other than internal ram even address other than internal ram odd address +1 +1 +1 +3 +2 +6 external data bus 8-bit +1 +3 +6 82 MB90246a series table 6 transmission instruction (byte) [50 instructions] note: for (a) and (b), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli + disp8 mov a, @sp + disp8 movp a, addr24 movp a, @a movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a, @rwi + disp8 movx a, @rli + disp8 movx a, @sp + disp8 movpx a, addr24 movpx a, @a mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli + disp8, a mov @sp + disp8, a movp addr24, a mov ri, ear mov ri, eam movp @a, ri mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2 + 2 2 2 3 3 5 2 1 2 3 2 2 2 + 2 2 2 2 3 3 5 2 2 3 1 2 2 + 2 3 3 5 2 2 + 2 2 2 + 2 3 3 3 3 + 2 2 2 + 2 2 + 2 2 1 1 2 + (a) 2 2 2 6 3 3 2 1 2 2 1 1 2 + (a) 2 2 2 3 6 3 3 2 2 2 1 2 2 + (a) 2 6 3 3 2 3 + (a) 3 3 3 + (a) 2 3 3 2 2 + (a) 2 3 3 + (a) 4 5 + (a) (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli) + disp8) byte (a) ? ((sp) + disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi) + disp8) byte (a) ? ((rli) + disp8) byte (a) ? ((sp) + disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) + disp8) ? (a) byte ((sp) + disp8) ? (a) byte (addr24) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte ((a)) ? (ri) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z z z z x x x x x x x x x x x x x C C C C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * C * * * * * * * * C * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 83 MB90246a series table 7 transmission instruction (word) [40 instructions] note: for (a) and (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi + disp8 movw a, @rli + disp8 movw a, @sp + disp8 movpw a, addr24 movpw a, @a movw dir, a movw addr16, a movw sp, #imm16 movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi + disp8, a movw @rli + disp8, a movw @sp + disp8, a movpw addr24, a movpw @a, rwi movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2 + 2 2 3 2 3 3 5 2 2 3 4 1 1 2 2 + 2 2 3 3 5 2 2 2 + 2 2 + 3 4 4 4 + 2 2 2 + 2 2 + 2 2 2 1 1 2 + (a) 2 2 2 3 6 3 3 2 2 2 2 2 1 2 2 + (a) 2 3 6 3 3 3 2 3 + (a) 3 3 + (a) 2 3 2 2 + (a) 2 3 3 + (a) 4 5 + (a) (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (a) ? ((sp) + disp8) word (a) ? (addr24) word (a) ? ((a)) word (dir) ? (a) word (addr16) ? (a) word (sp) ? imm16 word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word ((sp) + disp8) ? (a) word (addr24) ? (a) word ((a)) ? (rwi) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 84 MB90246a series table 8 transmission instruction (long) [11 instructions] note: for (a) and (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw movl a, ear 2 2 0 long (a) ? (ear) CCCCC* *CC C movl a, eam 2 + 3 + (a) (d) long (a) ? (eam) CCCCC* *CC C movl a, #imm32 5 3 0 long (a) ? imm32 CCCCC* *CC C movl a, @sp + disp8 3 4 (d) long (a) ? ((sp) + disp8) CCCCC* *CC C movpl a, addr24 5 4 (d) long (a) ? (addr24) CCCCC* *CC C movpl a, @a 2 3 (d) long (a) ? ((a)) CCCCC* *CC C movpl @a, rli 2 5 (d) long ((a)) ? (rli) CCCCC* *CC C movl @sp + disp8, a 3 4 (d) long ((sp) + disp8) ? (a) CCCCC* *CC C movpl addr24, a 5 4 (d) long (addr24) ? (a) CCCCC* *CC C movl ear, a 2 2 0 long (ear) ? (a) CCCCC* *CC C movl eam, a 2 + 3 + (a) (d) long (eam) ? (a) CCCCC* *CC C 85 MB90246a series table 9 add/subtract (byte, word, long) [42 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2 + 2 2 + 1 2 2 + 1 2 2 2 2 + 2 2 + 1 2 2 + 1 2 3 2 3 + (a) 2 3 + (a) 2 2 3 + (a) 3 2 3 2 3 + (a) 2 3 + (a) 2 2 3 + (a) 3 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) C imm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C C C * * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2 + 3 2 2 + 2 2 + 1 2 2 + 3 2 2 + 2 2 + 2 2 3 + (a) 2 2 3 + (a) 2 3 + (a) 2 2 3 + (a) 2 2 3 + (a) 2 3 + (a) 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) + (ear) word (a) ? (a) + (eam) word (a) ? (a) + imm16 word (ear) C (ear) + (a) word (eam) C (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) C imm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C * * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2 + 5 2 2 + 5 5 6 + (a) 4 5 6 + (a) 4 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) + imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) C imm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C 86 MB90246a series table 10 increment/decrement (byte, word, long) [12 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. table 11 compare (byte, word, long) [11 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw inc ear inc eam dec ear dec eam 2 2 + 2 2 + 2 3 + (a) 2 3 + (a) 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incw ear incw eam decw ear decw eam 2 2 + 2 2 + 2 3 + (a) 2 3 + (a) 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incl ear incl eam decl ear decl eam 2 2 + 2 2 + 4 5 + (a) 4 5 + (a) 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * * * mnemonic # ~ b operation lh ah istnzvcrmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2 + 2 1 2 3 + (a) 2 0 0 (b) 0 byte (ah) C (al) byte (a) C (ear) byte (a) C (eam) byte (a) C imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2 + 3 1 2 3 + (a) 2 0 0 (c) 0 word (ah) C (al) word (a) C (ear) word (a) C (eam) word (a) C imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2 + 5 6 7 + (a) 3 0 (d) 0 word (a) C (ear) word (a) C (eam) word (a) C imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C 87 MB90246a series table 12 unsigned multiply/division (word, long) [11 instructions] note: for (b) and (c), refer to table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation. *2: set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation. *3: set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation. *4: set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation. *5: set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation. *6: when the division-by-0, (b) for an overflow, and 2 (b) for normal operation. *7: when the division-by-0, (c) for an overflow, and 2 (c) for normal operation. *8: set to 3 when byte (ah) is zero, 7 when byte (ah) is not zero. *9: set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero. *10:set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero. *11:set to 3 when word (ah) is zero, 11 when word (ah) is not zero. *12:set to 4 when word (ear) is zero, 11 when word (ear) is not zero. *13:set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero. mnemonic # ~ b operation lh ah istnzvcrmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2 + 2 2+ 1 2 2 + 1 2 2 + *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C 88 MB90246a series table 0 signed multiplication/division (word, long) [11 instructions] for (b) and (c), refer to table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation. *2: set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation. *3: set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. *4: positive divided: set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation. negative divided: set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation. *5: positive divided: set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. negative divided: set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: set to (b) when the division-by-0 or an overflow, and 2 (b) for normal operation. *7: set to (c) when the division-by-0 or an overflow, and 2 (c) for normal operation. *8: set to 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10:set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11:set to 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12:set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13:set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. note: when overflow occurs during div or divw instruction execution, the number of execution cycles takes two values because of detection before and after an operation. when overflow occurs during div or divw instruction execution, the contents of al are destroyed. mnemonic # ~ b operation lh ah istnzvcrmw div a 2 *1 0word (ah)/byte (al) zCCCCCC* * C quotient ? byte (al) remainder ? byte (ah) div a, ear 2 *2 0word (a)/byte (ear) zCCCCCC* * C quotient ? byte (a) remainder ? byte (ear) div a, eam 2 +*3*6word (a)/byte (eam) zCCCCCC* * C quotient ? byte (a) remainder ? byte (eam) divw a, ear 2 *4 0long (a)/word (ear) CCCCCCC* * C quotient ? word (a) remainder ? word (ear) divw a, eam 2 +*5*7long (a)/word (eam) CCCCCCC* * C quotient ? word (a) remainder ? word (eam) mul a 2 *8 0 byte (ah) byte (al) ? word (a)CCCCCCCCC C mul a, ear 2 *9 0 byte (a) byte (ear) ? word (a) CCCCCCCCC C mul a, eam 2 + *10 (b) byte (a) byte (eam) ? word (a) CCCCCCCCC C mulw a 2 *11 0 word (ah) word (al) ? long (a) CCCCCCCCC C mulw a, ear 2 *12 0 word (a) word (ear) ? long (a) CCCCCCCCC C mulw a, eam 2 + *13 (b) word (a) word (eam) ? long (a) CCCCCCCCC C 89 MB90246a series table 14 logic 1 (byte, word) [39 instructions ] note: for (a) to (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2 + 2 2 + 2 2 2 + 2 2 + 2 2 2 + 2 2 + 1 2 2 + 2 2 3 + (a) 3 3 + (a) 2 2 3 + (a) 3 3 + (a) 2 2 3 + (a) 3 3 + (a) 2 2 3 + (a) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C * * C C C * * C C C * * C * * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2 + 2 2 + 1 3 2 2 + 2 2 + 1 3 2 2 + 2 2 + 1 2 2 + 2 2 2 3 + (a) 3 3 + (a) 2 2 2 3 + (a) 3 3 + (a) 2 2 2 3 + (a) 3 3 + (a) 2 3 3 + (a) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C * * C C C C * * C C C C * * C * * 90 MB90246a series table 15 logic 2 (long) [6 instructions] note: for (a) and (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. table 16 sign reverse (byte, word) [6 instructions] note: for (a) and (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. table 17 absolute values (byte, word, long) [3 instructions] table 18 normalize instruction (long) [1 instruction] * : set to 5 when the accumulator is all 0, otherwise set to 5 + (r0). mnemonic # ~ b operation lh ah istnzvcrmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ear xorl a, eam 2 2 + 2 2 + 2 2 + 5 6 + (a) 5 6 + (a) 5 6 + (a) 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg boperation lh ah istnzvc rmw neg a neg ear neg eam 1 2 2 + 2 3 5 + (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2 + 2 3 5 + (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ b operation lh ah istnzvcrmw abs a absw a absl a 2 2 2 2 2 4 0 0 0 byte (a) ? absolute value (a) word (a) ? absolute value (a) long (a) ? absolute value (a) z C C C C C C C C C C C C C C * * * * * * * * * C C C C C C mnemonic # ~ rg b operation lh ah istnzvc rmw nrml a, r0 2 *1 1 0 long (a) ? shift to where 1 is originally located byte (r0) ? number of shifts in the operation CCCCCC*CC C 91 MB90246a series table 19 shift type instruction (byte, word, long) [27 instructions] note: for (a) and (b), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 when r0 is 0, otherwise 3 + (r0). *2: set to 3 when r0 is 0, otherwise 4 + (r0). *3: set to 3 when imm8 is 0, otherwise 3 + imm8. *4: set to 3 when imm8 is 0, otherwise 4 + imm8. mnemonic # ~ b operation lh ah istnzvc rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 asr a, #imm8 lsr a, #imm8 lsl a, #imm8 2 2 2 2 + 2 2 + 2 2 2 3 3 3 2 2 2 3 + (a) 2 3 + (a) *1 *1 *1 *3 *3 *3 0 0 0 2 (b) 0 2 (b) 0 0 0 0 0 0 byte (a) ? with right-rotate carry byte (a) ? with left-rotate carry byte (ear) ? with right-rotate carry byte (eam) ? with right-rotate carry byte (ear) ? with left-rotate carry byte (eam) ? with left-rotate carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) byte (a) ? arithmetic right barrel shift (a, imm8) byte (a) ? logical right barrel shift (a, imm8) byte (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C * * * * * * * * * * * * C C * * * * C C C C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 asrw a, #imm8 lsrw a, #imm8 lslw a, #imm8 1 1 1 2 2 2 3 3 3 2 2 2 *1 *1 *1 *3 *3 *3 0 0 0 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) word (a) ? arithmetic right barrel shift (a, imm8) word (a) ? logical right barrel shift (a, imm8) word (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * C * r * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 asrl a, #imm8 lsrl a, #imm8 lsll a, #imm8 2 2 2 3 3 3 *2 *2 *2 *4 *4 *4 0 0 0 0 0 0 long (a) ? arithmetic right barrel shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) long (a) ? arithmetic right barrel shift (a, imm8) long (a) ? logical right barrel shift (a, imm8) long (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * C C C C C C * * * * * * C C C C C C 92 MB90246a series table 20 branch 1 [31 instructions] note: for (a), (c) and (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 when branch is executed, and 2 when branch is not executed. *2: 3 (c) + (b) *3: reads (word) of the branch destination address. *4: w pushes to stack (word), and r reads (word) of the branch destination address. *5: pushes to stack (word). *6: w pushes to stack (long), and r reads (long) of the branch destination address. *7: pushes to stack (long). mnemonic # ~ b operation lh ah istnzvcrmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @ a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2 + 2 2 + 4 2 2 + 3 1 2 2 + 4 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 2 3 4 + (a) 3 4 + (a) 3 4 5 + (a) 5 5 7 8 + (a) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) *2 2 (c) branch if (z) = 1 branch if (z) = 0 branch if (c) = 1 branch if (c) = 0 branch if (n) = 1 branch if (n) = 0 branch if (v) = 1 branch if (v) = 0 branch if (t) = 1 branch if (t) = 0 branch if (v) xor (n) = 1 branch if (v) xor (n) = 0 branch if ((v) xor (n)) or (z) = 1 branch if ((v) xor (n)) or (z) = 0 branch if (c) or (z) = 1 branch if (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear + 2) word (pc) ? (eam), (pcb) ? (eam + 2) word (pc) ? ad24 0 C 15, (pcb) ? ad24 16 C 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 C 15 (pcb) ? (ear) 16 C 23 word (pc) ? (eam) 0 C 15 (pcb) ? (eam) 16 C 23 word (pc) ? addr0 C 15, (pcb) ? addr16 C 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 93 MB90246a series table 21 branch 2 [20 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 4 when branch is executed, and 3 when branch is not executed. *2: set to 5 when branch is executed, and 4 when branch is not executed. *3: set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed. *4: set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed. *5: set to 3 (b) + 2 (c) when an interrupt request is issued, and 6 (c) for return. *6: this is a high-speed interrupt return instruction. in the instruction, an interrupt request is detected. when an interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector. *7: return from stack (word). *8: return from stack (long). mnemonic # ~ b operation lh ah istnzvcrmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel cwbne ear, #imm16, rel cwbne eam, #imm16, rel dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti retiq * 6 link #imm8 unlink ret * 7 retp * 8 3 4 4 4 + 5 5 + 3 3 + 3 3 + 2 3 4 1 1 2 2 1 1 1 *1 *1 *1 *3 *1 *3 *2 *4 *2 *4 14 12 13 14 9 11 6 5 4 5 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) *5 (c) (c) (c) (d) branch if byte (a) 1 imm8 branch if word (a) 1 imm16 branch if byte (ear) 1 imm8 branch if byte (eam) 1 imm8 branch if word (ear) 1 imm16 branch if word (eam) 1 imm16 byte (ear) = (ear) C 1, branch if (ear) 1 0 byte (eam) = (eam) C 1, branch if (eam) 1 0 word (ear) = (ear) C 1, branch if (ear) 1 0 word (eam) = (eam) C 1, branch if (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt return from interrupt stores old frame pointer in the beginning of the function, set new frame pointer, and reserves local pointer area restore old frame pointer from stack in the end of the function return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * * C C C C C C C C C C C C C C s s s s * * C C C C C C C C C C C C C C C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * C C C C C C C C * * C C C C C C C C C C C * C * C C C C C C C C C C 94 MB90246a series table 22 miscellaneous control types (byte, word, long) [36 instructions] note: for (a) and (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: pcb, adb, ssb, usb, and spb : 1 state dtb : 2 states dpr : 3 states *2: 3 + 4 (number of pops) mnemonic # ~ b operation lh ah istnzvcrmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a mov brg2, #imm8 nop adb dtb pcb spb ncc cmr movw spcu, #imm16 movw spcl, #imm16 setspc clrspc btscn a btscns a btscnd a 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2 + 2 2 + 2 3 2 2 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 3 3 3 *3 3 3 3 *2 9 3 3 2 2 3 2 + (a) 2 1 + (a) 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7 (c) (c) (c) *4 (c) (c) (c) *4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C 2, ((sp)) ? (a) word (sp) ? (sp) C 2, ((sp)) ? (ah) word (sp) ? (sp) C 2, ((sp)) ? (ps) (ps) ? (ps) C 2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) + 2 word (ah) ? ((sp)), (sp) ? ( sp) + 2 word (ps) ? ((sp)), (sp) ? ( sp) + 2 (rlst) ? ((sp)), (sp) ? (sp) + 2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) + ext (imm8) word (sp) ? (sp) + imm16 byte (a) ? (brgl) byte (brg2) ? (a) byte (brg2) ? imm8 no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no change in flag prefix for common register bank word (spcu) ? (imm16) word (spcl) ? (imm16) enables stack check operation. disables stack check operation. bit position of 1 in byte (a) from word (a) bit position ( 2) of 1 in byte (a) from word (a) bit position ( 4) of 1 in byte (a) from word (a) C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C C z z z C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C * * * C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 95 MB90246a series *3: 3 + 4 (number of pushes) *4: (number of pops) (c), or (number of pushes) (c) *5: set to 3 when al is 0, 5 when al is not 0. *6: set to 4 when al is 0, 6 when al is not 0. *7: set to 5 when al is 0, 7 when al is not 0. table 23 bit manipulation instruction [21 instructions] note: for (b), refer to table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 5 when branch is executed, and 4 when branch is not executed. *2: 7 if conditions are met, 6 when conditions are not met. *3: indeterminate times *4: until conditions are met mnemonic # ~ b operation lh ah istnzvcrmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) *4 *4 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch if (dir:bp) b = 0 branch if (addr16:bp) b = 0 branch if (io:bp) b = 0 branch if (dir:bp) b = 1 branch if (addr16:bp) b = 1 branch if (io:bp) b = 1 branch if (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C 96 MB90246a series table 24 accumulator manipulation instruction (byte, word) [6 instructions] table 25 string instruction [10 instructions] m: rw0 value (counter value) *1: 3 when rw0 is 0, 2 + 6 (rw0) when count out, and 6n + 4 when matched *2: 4 when rw0 is 0, otherwise 2 + 6 (rw0) *3: (b) (rw0) *4: (b) n *5: (b) (rw0) *6: (c) (rw0) *7: (c) n *8: (c) (rw0) mnemonic # ~ b operation lh ah istnzvcrmw swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 byte (a) 0 C 7 ? (a) 8 C 15 word (ah) ? (al) byte sign-extension word sign-extension byte zero-extension word zero-extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ b operation lh ah istnzvcrmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 *2 *2 *1 *1 5m + 6 *3 *3 *4 *4 *5 byte transfer @ah + ? @al +, counter = rw0 byte transfer @ah C ? @al C, counter = rw0 byte search (@ah +) C al, counter = rw0 byte search (@ah C) C al, counter = rw0 byte fill @ah + ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 *2 *2 *1 *1 5m + 6 *6 *6 *7 *7 *8 word transfer @ah + ? @al +, counter = rw0 word transfer @ah C ? @al C, counter = rw0 word search (@ah +) C al, counter = rw0 word search (@ah C) C al, counter = rw0 word fill @ah + ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C 97 MB90246a series table 26 multiple data transfer instructions [18 instruction] *1: 256 when 5 + imm8 5, imm8 is 0. *2: 256 when 5 + imm8 5 + (a), imm8 is 0. *3: (number of transfer cycles) (b) 2 *4: (number of transfer cycles) (c) 2 *5: the bank register specified by bnk is the same as that for the movs instruction. mnemonic # ~ b operation lh ah istnzvcrmw movm @a, @rli, #imm8 3 *1 *3 multiple data transfer byte ((a)) ? ((rli)) CCCCCCCCC C movm @a, eam, #imm8 3 + *2 *3 multiple data transfer byte ((a)) ? (eam) CCCCCCCCC C movm addr16, @rli, #imm8 5 *1 *3 multiple data transfer byte (addr16) ? ((rli)) CCCCCCCCC C movm addr16, @eam, #imm8 5 + *2 *3 multiple data transfer byte (addr16) ? (eam) CCCCCCCCC C movmw @a, @rli, #imm8 3 *1 *4 multiple data transfer word ((a)) ? ((rli)) CCCCCCCCC C movmw @a, eam, #imm8 3 + *2 *4 multiple data transfer word ((a)) ? (eam) CCCCCCCCC C movmwaddr16, @rli, #imm8 5 *1 *4 multiple data transfer word (addr16) ? ((rli)) CCCCCCCCC C movmwaddr16, @eam, #imm8 5 + *2 *4 multiple data transfer word (addr16) ? (eam) CCCCCCCCC C movm @rli, @a, #imm8 3 *1 *3 multiple data transfer byte ((rli)) ? ((a)) CCCCCCCCC C movm @eam, a, #imm8 3 + *2 *3 multiple data transfer byte (eam) ? ((a)) CCCCCCCCC C movm @rli, addr16, #imm8 5 *1 *3 multiple data transfer byte ((rli)) ? (addr16) CCCCCCCCC C movm @eam, addr16, #imm8 5 + *2 *3 multiple data transfer byte (eam) ? (addr16) CCCCCCCCC C movmw @rli, @a, #imm8 3 *1 *4 multiple data transfer word ((rli)) ? ((a)) CCCCCCCCC C movmw @eam, a, #imm8 3 + *2 *4 multiple data transfer word (eam) ? ((a)) CCCCCCCCC C movmw@rli, addr16, #imm8 5 *1 *4 multiple data transfer word ((rli)) ? (addr16) CCCCCCCCC C movmw@eam, addr16, #imm8 5 + *2 *4 multiple data transfer word (eam) ? (addr16) CCCCCCCCC C movm bnk: addr16, bnk: addr16, #imm8 * 5 7 *1 *3 multiple data transfer byte (bnk: addr16) ? (bnk: addr16) CCCCCCCCC C movmw bnk: addr16, bnk: addr16, #imm8 * 5 7 *1 *4 multiple data transfer word (bnk: addr16) ? (bnk: addr16) CCCCCCCCC C 98 MB90246a series n ordering information part number package remarks MB90246apfv 100-pin plastic lqfp (fpt-100p-m05) 99 MB90246a series n package dimensions c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. (mounting height) 100-pin plastic lqfp (fpt-100p-m05) dimensions in mm (inches) MB90246a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f98010 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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